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AD9548/PCBZ 数据表(PDF) 94 Page - Analog Devices |
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AD9548/PCBZ 数据表(HTML) 94 Page - Analog Devices |
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94 / 112 page  AD9548 Rev. 0 | Page 94 of 112 Register 0A03—ResetFunc Table 121. Reset Functions1 Address Bits Bit Name Description 0A03 [7] Unused [6] Clear LF Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). [5] Clear CCI Setting this bit (default = 0) clears the CCI filter (intended as a debug tool). [4] Clear phase accumulator Setting this bit (default = 0) clears DDS phase accumulator (not a recommended action). [3] Reset auto sync Setting this bit (default = 0) resets the automatic synchronization logic (see Register 0403). [2] Reset TW history Setting this bit (default = 0) resets the tuning word history logic (part of holdover functionality). [1] Reset all IRQs Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0D02 to Register 0D09). It is the equivalent of setting all the bits of the IRQ clearing register (Register 0A04 to Register 0A0B). [0] Reset watchdog Setting this bit (default = 0) resets the watchdog timer (see Register 0211 to Register 0212). If the timer had timed out, it simply starts a new timing cycle. If the timer has not yet timed out, it restarts at time zero without causing a timeout event. Continuously resetting the watchdog timer at intervals less than its timeout period prevents the watchdog timer from generating a timeout event. 1 All bits in this register are autoclearing. Register 0A04 to Register 0A0B—IRQ Clearing The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0D02 to Address 0D09). When set to Logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing register is an autoclearing register. Table 122. IRQ Clearing for SYSCLK Address Bits Bit Name Description 0A04 [7:6] Unused [5] SYSCLK unlocked Clears SYSCLK unlocked IRQ [4] SYSCLK locked Clears SYSCLK locked IRQ [3:2] Unused [1] SYSCLK Cal complete Clears SYSCLK calibration complete IRQ [0] SYSCLK Cal started Clears SYSCLK calibration started IRQ Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM Address Bits Bit Name Description 0A05 [7:4] Unused [3] Distribution sync Clears distribution sync IRQ [2] Watchdog timer Clears watchdog timer IRQ [1] EEPROM fault Clears EEPROM fault IRQ [0] EEPROM complete Clears EEPROM complete IRQ Table 124. IRQ Clearing for the Digital PLL Address Bits Bit Name Description 0A06 [7] Switching Clears switching IRQ [6] Closed Clears closed IRQ [5] Freerun Clears freerun IRQ [4] Holdover Clears holdover IRQ [3] Freq unlocked Clears frequency unlocked IRQ [2] Freq locked Clears frequency locked IRQ [1] Phase unlocked Clears phase unlocked IRQ [0] Phase locked Clears phase locked IRQ |
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