AD9548SLASHPCBZ datasheet(33/112 Pages) AD

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AD9548

Rev. 0 | Page 33 of 112

(Address 030F to Address 0313). The 40-bit word is a signed

(twos complement) number that represents units of picoseconds.

In addition, the user can adjust the closed-loop phase offset

(positive or negative) in incremental fashion. To do so, program

the desired step size in the 16-bit incremental phase lock offset

step size register (Address 0314 to Address 0315). This is an

unsigned number that represents units of picoseconds. The

programmed step size is added to the current closed-loop phase

offset each time the user writes a Logic 1 to the increment phase

offset bit (Register 0A0C, Bit 0). Conversely, the programmed

step size is subtracted from the current closed-loop phase offset

each time the user writes a Logic 1 to the decrement phase offset

bit (Register 0A0C, Bit 1). The serial I/O port control logic clears

both of these bits automatically. The user can remove the incre-

mentally accumulated phase by writing a Logic 1 to the reset

incremental phase offset bit (Register 0A0C, Bit 2), which is

also cleared automatically. Alternatively, rather than using the

serial I/O port, the multifunction pins can be set up to perform

the increment, decrement, and clear functions.

Note that the incremental phase offset is completely indepen-

dent of the offset programmed into the fixed phase lock offset

Hitless Reference Switching (Phase Slew Control) section), then

any instantaneous change in closed-loop phase offset (fixed or

incremental) will be subject to possible slew limitation by the

action of the phase slew limiter.

Programmable Digital Loop Filter

The AD9548 loop filter is a third order digital IIR filter that is

analogous to the third order analog loop shown in Figure 39.

Figure 39. Third Order Analog Loop Filter

The filter requires four coefficients as shown in Figure 40. The

AD9548 evaluation board software automatically generates the

required loop filter coefficient values based on the user’s design

criteria. The Calculating Digital Filter Coefficients section

contains the design equations for calculating the loop filter

coefficients manually.

LOOP FILTER

(THIRD ORDER IIR)

OUT

FRACTIONAL

(16-BIT)

1/2x

(6-BIT)

(3-BIT)

(4-BIT)

FRACTIONAL

(17-BIT)

1/2x

(6-BIT)

FRACTIONAL

(17-BIT)

1/2x

(6-BIT)

FRACTIONAL

(15-BIT)

1/2x

(5-BIT)

Figure 40. Third Order Digital IIR Loop Filter

Each coefficient has a fractional component representing a

value from 0 up to, but not including, unity. Each coefficient

also has an exponential component representing a power of 2

with a negative exponent. That is, the user enters a positive

number (x) that the hardware interprets as a negative exponent

of two (2−x). Thus, the β, γ, and δ coefficients always represent

values less than unity. The α coefficient, however, has two

additional exponential components, but the hardware interprets

these as a positive exponent of 2 (that is, 2x). This allows the α

coefficient to be a value greater than unity. The positive

exponent appears as two separate terms in order to provide

sufficient dynamic range.

DPLL Phase Lock Detector

The DPLL contains an all-digital phase lock detector. The user

controls the threshold sensitivity and hysteresis of the phase

detector via the profile registers.

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 41). The total capacity of the tub is

4096 units with −2048 denoting empty, 0 denoting the 50%

point, and +2048 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark at

−1024 and a high water mark at +1024. To change the water

level, the user adds water with a fill bucket or removes water

with a drain bucket. The user specifies the size of the fill and

drain buckets via the 8-bit fill rate and drain rate values in the

profile registers.

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. Whenever the water

level is below the low water mark (−1024), the detector

indicates an unlock condition. Conversely, whenever the water

level is above the high water mark (+1024), the detector indicates

a lock condition. While the water level is between the marks,

the detector simply holds its last condition. This concept appears

graphically in Figure 41, with an overlay of an example of the

instantaneous water level (vertical) vs. time (horizontal) and the

resulting lock/unlock states.

During any given PFD phase error sample, the detector either

adds water with the fill bucket or removes water with the drain

bucket (one or the other but not both). The decision of whether

to add or remove water depends on the threshold level specified

by the user. The phase lock threshold value is a 16-bit number

stored in the profile registers and is expressed in picoseconds.

Thus, the phase lock threshold extends from 0 ns to ±65.535 ns

and represents the magnitude of the phase error at the output of

the PFD.

The phase lock detector compares each phase error sample at

the output of the PFD to the programmed phase threshold

value. If the absolute value of the phase error sample is less than

or equal to the programmed phase threshold value, then the

detector control logic dumps one fill bucket into the tub.

Otherwise, it removes one drain bucket from the tub. Notice

that it is not the polarity of the phase error sample, but its

magnitude relative to the phase threshold value, that determines

whether to fill or drain. If more filling is taking place than

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