AD9548SLASHPCBZ datasheet(54/112 Pages) AD

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AD9548

Rev. 0 | Page 54 of 112

DATA BIT N – 1

DATA BIT N

SCLK

SDIO

SDO

tDV

Figure 56. Timing Diagram for Serial Control Port Register Read

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1

A9 A10 A11 A12

R/W

D5 D6

Figure 57. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

SCLK

SDIO

tHI

tLO

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 58. Serial Control Port Timing—Write

Table 32. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK

tDH

Hold time between data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

tDV

SCLK to valid SDIO and SDO (see Figure 56)

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