AD9548SLASHPCBZ datasheet(31/112 Pages) AD

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AD9548

Rev. 0 | Page 31 of 112

ACTIVE

A FAULTED

B FAULTED

ALL VALID

INITIAL

STATE

A VALID

B VALID

A VALID

B VALID

INPUT

PRIORITY

PROMOTED

PRIORITY TABLE

COMMON

WITHOUT PROMOTION

WITH PROMOTION

Figure 35. Example of Priority Promotion

PROFILE

SELECTION

VALIDATION

LOGIC

PRIORITY

SELECTION

÷R

MONITORS

A/AA

B/BB

C/CC

D/DD

TDC

LOOP

CONTROLLER

Figure 36. Reference Clock Block Diagram

Phase Build-Out Reference Switching

Phase build-out reference switching is the term given to a

reference switchover that completely masks any phase

difference between the previous reference and the new

reference. That is, there is virtually no phase change detectable

at the output when a phase build-out switchover occurs.

The AD9548 handles phase build-out switching based on

whether the new reference is a phase master. A phase master is

any reference with a selection priority value that is less than the

phase master threshold priority value (that is, higher priority).

The phase master threshold priority value resides in the phase

build-out switching register (Address 0507), whereas the

selection priority resides in the profile registers (Address 0600

to Address 07FF). By default, the phase master threshold

priority is 0; therefore, no references can be phase masters until

the user changes the phase master threshold priority.

Whenever the AD9548 switches from one reference to another,

it compares the selection priority value stored in the profile

assigned to the new reference with the phase master threshold

priority. The AD9548 performs a phase build-out switchover

only if the new reference is not a phase master.

Hitless Reference Switching (Phase Slew Control)

Hitless reference switching is the term given to a reference

switchover that limits the rate of change of the phase of the

output clock while the PLL is in the process of acquiring phase

lock. This prevents the output frequency offset from becoming

excessive.

The all-digital nature of the DPLL core (see the Digital PLL

(DPLL) Core section) gives the user numerical control of the

rate at which phase changes occur at the DPLL output. When

enabled, a phase slew controller monitors the phase difference

between the feedback and reference inputs to the DPLL. The

phase slew controller has the ability to place a user-specified

limit on the rate of change of phase, thus providing a

mechanism for hitless reference switching.

The user sets a limit on the rate of change of phase by storing

the appropriate value in the 16-bit phase slew rate limit register

(Address 0316 to Address 0317). The 16-bit word (representing

ns/sec) puts an upper bound on the rate of change of the phase

at the output of the DPLL during a reference switchover. A

phase slew rate value of 0 (default) disables the phase slew

controller.

The accuracy of the phase slew controller depends on both the

phase slew limit value and the system clock frequency.

Generally, an increase in the phase slew rate limit value or a

decrease in the system clock frequency tends to reduce the

error. As such, the accuracy is best for the largest phase slew

limit value and the lowest system clock frequency. For example,

assuming the use of a 1 GHz system clock, a phase slew limit

value of 315 ns/sec (or more) ensures an error of less than 10%,

whereas a phase slew rate limit value above ~3100 ns/sec

ensures an error of less than 1%. On the other hand, assuming

the use of a 500 MHz system clock, the same phase slew rate

limit values ensure an error of less than 5% or 0.5%,

respectively.

AD9548/PCBZ 数据表(PDF) 31 Page - Analog Devices

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