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AD9548/PCBZ 数据表(PDF) 12 Page - Analog Devices |
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AD9548/PCBZ 数据表(HTML) 12 Page - Analog Devices |
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12 / 112 page  AD9548 Rev. 0 | Page 12 of 112 Parameter Min Typ Max Unit Test Conditions/Comments SDA (AS OUTPUT) Output Logic 0 Voltage 0.4 V IO = 3 mA. Output Fall Time from VIHmin to VILmax 20 + 0.1 Cb1 250 ns 10 pF ≤ Cb ≤ 400 pF. TIMING SCL Clock Rate 400 kHz Bus-Free Time Between a Stop and Start Condition, tBUF 1.3 μs Repeated Start Condition Setup Time, tSU; STA 0.6 μs Repeated Hold Time Start Condition, tHD;STA 0.6 μs After this period, the first clock pulse is generated. Stop Condition Setup Time, tSU; STO 0.6 μs Low Period of the SCL Clock, tLO 1.3 μs High Period of the SCL Clock, tHI 0.6 μs SCL/SDA Rise Time, tR 20 + 0.1 Cb1 300 ns SCL/SDA Fall Time, tF 20 + 0.1 Cb1 300 ns Data Setup Time, tSU; DAT 100 ns Data Hold Time, tHD; DAT 100 ns Capacitive Load for Each Bus Line, Cb1 400 pF 1 Cb is the capacitance (pF) of a single bus line. JITTER GENERATION Table 19. Parameter Min Typ Max Unit Test Conditions/Comments JITTER GENERATION fREF = 1 Hz1; fDDS = 122.88 MHz2; fLOOP = 0.01 Hz3 fSYSCLK = 20 MHz4 OCXO; fS = 1 GHz5; Q- divider = 1; default SysClk PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Bandwidth: 100 Hz to 61 MHz 0.81 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.73 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.79 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.78 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.37 ps rms Random jitter fREF = 8 kHz1; fDDS = 155.52 MHz2; fLOOP = 100 Hz3 fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5; Q-divider = 1; default SYSCLK PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Bandwidth: 100 Hz to 77 MHz 0.71 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.34 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.31 ps rms Random jitter fREF = 19.44 MHz1; fDDS = 155.52 MHz2; fLOOP = 1 kHz3 fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5; Q-divider = 1; default SYSCLK PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Bandwidth: 100 Hz to 77 MHz 1.05 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.34 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.32 ps rms Random jitter |
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