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AD9548/PCBZ 数据表(PDF) 4 Page - Analog Devices |
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AD9548/PCBZ 数据表(HTML) 4 Page - Analog Devices |
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4 / 112 page  AD9548 Rev. 0 | Page 4 of 112 SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25°C; IDAC = 20 mA (full scale), unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD3 3.135 3.30 3.465 V Pin 7, Pin 82 DVDD 1.71 1.80 1.89 V Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88 AVDD3 3.135 3.30 3.465 V Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73 3.3 V Supply (Typical) 3.135 3.30 3.465 V Pin 31, Pin 37, Pin 38, Pin 44 1.8 V Supply (Alternative) 1.71 1.80 1.89 V Pin 31, Pin 37, Pin 38, Pin 44 AVDD 1.71 1.80 1.89 V Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59, Pin 63, Pin 70, Pin 74 SUPPLY CURRENT The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3. The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT IDVDD3 1.5 3 mA Pin 7, Pin 82 IDVDD 190 215 mA Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88 IAVDD3 52 75 mA Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73 IAVDD3 3.3 V Supply (Typical) 24 110 mA Pin 31, Pin 37, Pin 38, Pin 44 1.8 V Supply (Alternative) 24 110 mA Pin 31, Pin 37, Pin 38, Pin 44 IAVDD 135 163 mA Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59, Pin 63, Pin 70, Pin 74 POWER DISSIPATION Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION Typical Configuration 800 1100 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 122.88 MHz3; one LVPECL clock distribution output running at 122.88 MHz (all others powered down); one input reference running at 100 MHz (all others powered down) All Blocks Running 900 1400 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock distribution outputs configured as LVPECL at 399 MHz; all input references configured as differential at 100 MHz; fractional-N active (R = 10, S = 39, U = 9, V = 10) Full Power-Down 13 mW Conditions = typical configuration; no external pull-up or pull-down resistors |
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