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AD9548/PCBZ 数据表(PDF) 5 Page - Analog Devices |
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AD9548/PCBZ 数据表(HTML) 5 Page - Analog Devices |
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5 / 112 page  AD9548 Rev. 0 | Page 5 of 112 Parameter Min Typ Max Unit Test Conditions/Comments Incremental Power Dissipation Conditions = typical configuration; table values show the change in power due to the indicated operation. SYSCLK PLL Off −105 mW fSYSCLK = 1 GHz1; high frequency direct input mode. Input Reference On Differential 7 mW Single-Ended 13 mW Output Distribution Driver On LVDS 70 mW LVPECL 75 mW CMOS 65 mW A single 3.3 V CMOS output with a 10 pF load. 1 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins. 2 fS is the sample rate of the output DAC. 3 fDDS is the output frequency of the DDS. LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS) Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS (M7 to M0, RESET, TDI, TCLK, TMS) Input High Voltage (VIH) 2.1 V Input Low Voltage (VIL) 0.8 V Input Current (IINH, IINL) ±80 ±200 μA Input Capacitance (CIN) 3 pF LOGIC OUTPUTS (M7 TO M0, IRQ, TDO) Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (M7 to M0, IRQ, TDO) Output High Voltage (VOH) 2.7 V IOH = 1 mA Output Low Voltage (VOL) 0.4 V IOL = 1 mA IRQ Leakage Current Open-drain mode Active Low Output Mode 1 μA VOH = 3.3 V Active High Output Mode 1 μA VOL =-0 V SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments SYSTEM CLOCK PLL BYPASSED Input Frequency Range 500 1000 MHz Minimum Input Slew Rate 1000 V/μs Minimum limit imposed for jitter performance Duty Cycle 40 60 % Common-Mode Voltage 1.2 V Internally generated Differential Input Voltage Sensitivity 100 mV p-p Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input Input Capacitance 2 pF Single-ended, each pin Input Resistance 2.5 kΩ |
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