AD9548SLASHPCBZ datasheet(32/112 Pages) AD

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AD9548

Rev. 0 | Page 32 of 112

DIGITAL PLL (DPLL) CORE

DPLL Overview

A diagram of the digital PLL core of the AD9584 appears in

Figure 37. The phase/frequency detector, feedback path, lock

detectors, phase offset, and phase slew rate limiting that

comprise this second generation DPLL are all digital

implementations.

R + 1

REF A

TDC

AND

PFD

DIGITAL

LOOP

FILTER

DDS/

DAC

DACOUT

CLOSED-LOOP

PHASE OFFSET

PHASE SLEW

LIMIT

LOCK

DETECT

REF DD

DPPL CORE

fTDC

fDDS

S + 1 + U/V

Figure 37. Digital PLL Core

The start of the DPLL signal chain is the reference signal, fR,

which is the frequency of the reference input. A reference

prescaler reduces the frequency of this signal by an integer factor,

R + 1, where R is the 30-bit value stored in the appropriate

profile register and 0 ≤ R ≤ 1,073,741,823. Therefore, the freq-

uency at the output of the R-divider (or the input to TDC) is

TDC

A time-to-digital converter (TDC) samples the output of the

R-divider. The TDC/PFD produces a time series of digital

words and delivers them to the digital loop filter. The digital

loop filter offers the following advantages:

•

Determination of the filter response by numeric

coefficients rather than by discrete component values

•

The absence of analog components (R/L/C), which

eliminates tolerance variations due to aging

•

The absence of thermal noise associated with analog

components

•

The absence of control node leakage current associated

with analog components (a source of reference feed-

through spurs in the output spectrum of a traditional

analog PLL)

The digital loop filter produces a time series of digital words at

its output and delivers them to the frequency tuning input of a

DDS, with the DDS replacing the function of the VCO in an

analog PLL. The digital words from the loop filter tend to steer

the DDS frequency toward frequency and phase lock with the

input signal (fTDC). The DDS provides an analog output signal

via an integrated DAC, effectively mimicking the operation of

an analog VCO.

The DPLL includes a feedback divider that causes the DDS to

operate at an integer-plus-fractional multiple (S + 1 + U/V) of

fTDC. S is the 30-bit value stored in the profile register and has

a range of 7 ≤ S ≤ 1,073,741,823. U and V are the 10-bit numer-

ator and denominator values of the optional fractional divide

component and are also stored in the profile register. Together

they establish the nominal DDS frequency (fDDS), given by

⎟

⎠

⎞

⎜

⎝

⎛

DDS

Normally, fractional-N designs exhibit distinctive phase noise

and spurious artifacts resulting from the modulation of the

integer divider based on the fractional value. Such is not the

case for the AD9548 because it uses a purely digital means to

determine phase errors. Because the phase errors incurred by

modulating the feedback divider are deterministic, it is possible

to compensate for them digitally. The result is a fractional-N

PLL with no discernable modulation artifacts.

TDC/PFD

The TDC is a highly integrated functional block that incor-

porates both analog and digital circuitry. There are two pins

associated with the TDC that the user must connect to external

components. Figure 38 shows the recommended component

values and their connections.

For best performance, place components as close as possible to

the device pins. Components with low effective series resistance

(ESR) and low parasitic inductance yield the best results.

AD9548

10µF

0.1µF

TDC_VRT

TDC_VRB

Figure 38. TDC Pin Connections

The phase-frequency detector (PFD) is an all-digital block. It

compares the digital output from the TDC (which relates to the

active reference edge) with the digital word from the feedback

block (which relates to the rollover edge of the DDS

accumulator after division by the feedback divider). It uses a

digital code pump and digital integrator (rather than a

conventional charge pump and capacitor) to generate the error

signal that steers the DDS frequency toward phase lock.

Closed-Loop Phase Offset

The all-digital nature of the TDC/PFD provides for numerical

control of the phase offset between the reference and feedback

edges. This allows the user to adjust the relative timing of the

distribution output edges relative to the reference input edges

by programming the 40-bit fixed phase lock offset register

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