数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AD9548/PCBZ 数据表(PDF) 10 Page - Analog Devices

部件名 AD9548/PCBZ
功能描述  Quad/Octal Input Network Clock Generator/Synchronizer
PDF  112 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9548/PCBZ 数据表(HTML) 10 Page - Analog Devices

Back Button AD9548/PCBZ Datasheet HTML 6Page - Analog Devices AD9548/PCBZ Datasheet HTML 7Page - Analog Devices AD9548/PCBZ Datasheet HTML 8Page - Analog Devices AD9548/PCBZ Datasheet HTML 9Page - Analog Devices AD9548/PCBZ Datasheet HTML 10Page - Analog Devices AD9548/PCBZ Datasheet HTML 11Page - Analog Devices AD9548/PCBZ Datasheet HTML 12Page - Analog Devices AD9548/PCBZ Datasheet HTML 13Page - Analog Devices AD9548/PCBZ Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 112 page
background image
AD9548
Rev. 0 | Page 10 of 112
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TIME DURATION OF DIGITAL FUNCTIONS
EEPROM-to-Register Download Time
25
ms
Using default EEPROM storage
sequence (see Register 0E10 to
Register 0E3F)
Register-to-EEPROM Upload Time
200
ms
Using default EEPROM storage
sequence (see Register 0E10 to
Register 0E3F
Minimum Power-Down Exit Time
10.5
μs
Dependent on loop-filter bandwidth
Maximum Time from Assertion of the RESET
pin to the M0 to M7 Pins Entering High
Impedance State
45
ns
DIGITAL PLL
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL PLL
Phase-Frequency Detector (PFD)
Input Frequency Range
1
107
Hz
Maximum fPFD1: fS/1002
Loop Bandwidth
0.001
105
Hz
Programmable design parameter; maximum
fLOOP = fREF/(20R)3
Phase Margin
30
89
Degrees
Programmable design parameter
Reference Input (R) Division Factor
1
230
1, 2, …, 1,073,741,824
Integer Feedback (S) Division Factor
8
230
8, 9, …, 1,073,741,824
Fractional Feedback Divide Ratio
0
0.999
Maximum value: 1022/1023.
1 fPFD is the frequency at the input to the phase-frequency detector.
2 fS is the sample rate of the output DAC.
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
0.001
65.5
ns
Threshold Resolution
1
ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
0.001
16,700
ns
Reference-to-feedback period difference
Threshold Resolution
1
ps
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Frequency Accuracy
<0.01
ppm
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com