AD9548SLASHPCBZ datasheet(39/112 Pages) AD

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AD9548

Rev. 0 | Page 39 of 112

To determine the external loop filter components, the user

decides on the desired open loop bandwidth (fOL) and phase

margin (φ). These parameters allow calculation of the loop filter

components, as follows:

()⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛

sin

VCO

()

()2

tan

VCO

()

() ⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛ −

cos

sin

VCO

where KVCO = 7 × 107 V/ns (typical), ICP is the programmed

charge pump current (amperes), N is the programmed feedback

divider value, fOL is the desired open-loop bandwidth (in hertz),

and Φ is the desired phase margin (in radians).

For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,

and Φ = 50°, then the loop filter calculations yield R1 = 3.31

kΩ, C1 = 330 pF, and C2 = 50.4 pF.

System Clock Stability Timer

The system clock stability timer (Register 0106 to Register 0108) is

a 20-bit value programmed in milliseconds. If the programmed

timer value is 0, then the timer immediately indicates that it has

timed out. If the programmed timer value is a nonzero value

and the SYSCLK PLL is enabled, then the timer starts timing

when the SYSCLK PLL lock detector indicates lock and times

out after the prescribed period. However, when the user

disables the SYSCLK PLL, then the timer ignores the SYSCLK

PLL lock detector and starts timing as soon as the SYSCLK PLL

is disabled. The user can monitor the status of the stability timer

via Register 0D01, Bit 4, via the multifunction pins or via the

IRQ pin.

Note that the system clock stability timer must be programmed

before the SYSCLK PLL is either activated or disabled.

SYSCLK PLL Calibration

When using the SYSCLK PLL, it is necessary to calibrate the LC

VCO to ensure that the PLL can remain locked to the system

clock input signal. Assuming the presence of either an external

SYSCLK input signal or a crystal resonator, the calibration

process executes after the user sets and then clears the calibrate

system clock bit in the cal/sync register (Register 0A02, Bit 0).

During the calibration process, the device calibrates the VCO

amplitude and frequency. The status of the system clock cali-

bration process is user accessible via the system clock register

(Register 0D01, Bit 1). It is also available via the IRQ monitor

via the IRQ mask register.

When the calibration sequence is complete, the SYSCLK PLL

eventually attains a lock condition, at which point the system

clock stability timer begins its countdown sequence. Expiration

of the timer indicates that the SYSCLK PLL is stable, which is

reflected in the system clock register (Register 0D01, Bit 4).

Note that the monitors/detectors associated with the input

references (REFA/AA – REFD/DD) are internally disabled until

the SYSCLK PLL indicates that it is stable.

CLOCK DISTRIBUTION

The clock distribution block of the AD9548 provides an

integrated solution for generating multiple clock outputs based

on frequency dividing the DPLL output. The distribution

output consists of four channels (OUT0 to OUT3). Each of the

four output channels has a dedicated divider and output driver,

as appears in Figure 47.

SYNC

CONTROL

ENABLEn/MODEn

SYNC SOURCE

CLKINP

OUT1P

OUT1N

OUT2P

OUT2N

OUT3P

OUT3N

OUT1

OUT3

OUT2

OUT0

CLKINN

OUT_RSET

OUT0P

OUT0N

Figure 47. Clock Distribution

Clock Input (CLKINx)

The clock input handles input signals from a variety of logic

families (assuming proper terminations and sufficient voltage

swing). It also handles sine wave input signals such as those

delivered by the DAC reconstruction filter. Its default operating

frequency range is 62.5 MHz to 500 MHz.

Super-Nyquist Operation

Typically, the maximum usable frequency at the DAC output is

about 45% of the system clock frequency. However, because it is

a sampled DAC, its output spectrum contains Nyquist images.

Of particular interest are the images appearing in the first Nyquist

zone (50% to 100% of the system clock frequency). Super-

Nyquist operation takes advantage of these higher frequencies,

but this implies that the CLKINx input operates in excess of

500 MHz, which is outside of its default operating limits.

The CLKINx receiver actually consists of two separate receivers:

the default receiver and an optional high frequency receiver,

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