AD9548SLASHPCBZ datasheet(41/112 Pages) AD

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AD9548

Rev. 0 | Page 41 of 112

of the channel have a dedicated CMOS driver. By default, both

drivers deliver identical signals. However, setting the CMOS

phase invert bit causes the signal on an OUTxN pin to be the

opposite of the signal appearing on the OUTxP pin.

The drive strength bit allows the user to control whether the

output uses weak (0) or strong (1) drive capability (applies to

CMOS and LVDS but not LVPECL). For the CMOS family, the

strong setting implies normal CMOS drive capability, whereas

the weak setting implies low capacitive loading and allows for

reduced EMI. For the LVDS family, the weak setting provides

3.5 mA drive current for standard LVDS operation, whereas the

strong setting provides 7 mA for double terminated or double

voltage LVDS operation. Note that 3.5 mA and 7 mA are the

nominal drive current values when using the internal current

setting resistor.

Output Current Control with an External Resistor

By default, the output drivers have an internal current setting

resistor (3.12 kΩ nominal) that establishes the nominal drive

current for the LVDS and LVPECL operating modes. Instead of

using the internal resistor, the user can set the external

distribution resistor bit (Register 0400, Bit 5) and connect an

external resistor to the OUT_RSET pin. Note that this feature

supports an external resistor value of 3.12 kΩ only, allowing for

tighter control of the output current than is possible by using

the internal current setting resistor. However, if the user elects

to use a nonstandard external resistance, the following

equations provide the output drive current as a function of the

external resistance (R):

LVDS

8325

0 =

LVDS

665

1 =

LVPECL

The numeric subscript associated with the LVDS output current

corresponds to the logic state of the drive strength bit in the

distribution channel modes register (Address 0404 to Address

0407). For R = 3.12 kΩ, the equations yield ILVDS0 = 3.5 mA,

ILVDS1 = 7.0 mA, and ILVPECL = 8.0 mA. Note that the device

maintains a constant 1.238 V (nominal) across the external

resistor.

Clock Distribution Synchronization

A block diagram of the distribution synchronization

functionality appears in Figure 48. The synchronization

sequence begins with the primary synchronization signal,

which ultimately results in delivery of a synchronization strobe

to the clock distribution logic.

As indicated, the primary synchronization signal originates

from four possible sources.

•

Direct sync source via the sync distribution bit (Register

0A02, Bit 1)

•

Automatic sync source based on frequency or phase lock

detection as controlled via the automatic synchronization

•

Multifunction pin sync source via one of the multifunction

pins (M0 to M7)

•

EEPROM sync source via the EEPROM

All four sources of the primary synchronization signal are logic

OR’d, so any one of them can synchronize the clock distribution

output at any time. When using the multifunction pins, the

synchronization event is the falling edge of the selected signal.

When using the sync distribution bit, the user sets and then

clears the bit. The synchronization event is the clearing

operation; that is, the Logic 1 to Logic 0 transition of the bit.

The primary synchronization signal can synchronize the distri-

bution output directly or it can enable a secondary synchronization

signal. This functionality depends on the two sync source bits in

the distribution synchronization register (Register 0402, Bits[5:4]).

When sync source = 00 (direct), the falling edge of the primary

synchronization signal synchronizes the distribution output

directly.

When sync source = 01, the rising edge of the primary synch-

ronization signal triggers the circuitry that detects a rising edge

of the active input reference. The detection of the rising edge is

what synchronizes the distribution output.

When sync source = 10, the rising edge of the primary synch-

ronization signal triggers the circuitry that detects a rollover of

the DDS accumulator (after processing by the DPLL feedback

divider). This corresponds to the zero crossing of the output of

the phase-to-amplitude converter in the DDS (less the open-

loop phase offset stored in Register 030D to Register 030E). The

detection of the DPLL feedback edge is what synchronizes the

distribution output.

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