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AD9548/PCBZ 数据表(PDF) 100 Page - Analog Devices |
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AD9548/PCBZ 数据表(HTML) 100 Page - Analog Devices |
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100 / 112 page ![]() AD9548 Rev. 0 | Page 100 of 112 Table 138. Input Reference Status Address Bits Bit Name Description 0D0C [7] Profile selected The control logic sets this bit when it assigns Ref A to one of the eight profiles. [6:4] Selected profile The index (0 to 7) of the profile assigned to Ref A. Note that these bits are meaningless unless Bit 7 = 1. [3] Valid Ref A is valid for use (it is unfaulted and its validation timer has expired). [2] Fault Ref A is not valid for use. [1] Fast If Bit 7 = 1, then this bit indicates that the frequency of Ref A is higher than allowed by its profile settings. If Bit 7 = 0, then this bit indicates that the frequency of Ref A is above the maximum input reference frequency supported by the device. [0] Slow If Bit 7 = 1, then this bit indicates that the frequency of Ref A is lower than allowed by its profile settings. If Bit 7 = 0, then this bit indicates that the frequency of Ref A is below the minimum input reference frequency supported by the device. 0D0D [7:0] Same as 0D0C but for REF AA instead of REF A. 0D0E [7:0] Same as 0D0C but for REF B instead of REF A. 0D0F [7:0] Same as 0D0C but for REF BB instead of REF A. 0D10 [7:0] Same as 0D0C but for REF C instead of REF A. 0D11 [7:0] Same as 0D0C but for REF CC instead of REF A. 0D12 [7:0] Same as 0D0C but for REF D instead of REF A. 0D13 [7:0] Same as 0D0C but for REF DD instead of REF A. Table 139. Holdover History1 Address Bits Bit Name Description 0D14 [7:0] Holdover history Tuning word readback, Bits[7:0] 0D15 [7:0] Tuning word readback, Bits[15:8] 0D16 [7:0] Tuning word readack, Bits[23:9] 0D17 [7:0] Tuning word readback, Bits[31:24] 0D18 [7:0] Tuning word readback, Bits[39:32] 0D19 [7:0] Tuning word readback, Bits[47:40] 1 These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic. NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0E00 TO REGISTER 0E03) Table 140. EEPROM Control Address Bits Bit Name Description 0E00 [7:2] Unused [1] Half rate mode EEPROM serial communication rate. 0 (default) = 400 kHz (normal). 1 = 200 kHz. [0] Write enable EEPROM write enable/protect. 0 (default) = EEPROM write protected. 1 = EEPROM write enabled. 0E01 [7:5] Unused [4:0] Condition value When set to a nonzero value (default = 0), these bits establish the condition for EEPROM downloads. 0E02 [7:1] Unused 0 Save to EEPROM Upload data to the EEPROM based on the EEPROM storage sequence. This is an autoclearing bit. 0E03 [7:2] Unused [1] Load from EEPROM Download data from the EEPROM. This is an autoclearing bit. [0] Unused |
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