AD9548SLASHPCBZ datasheet(58/112 Pages) AD

58 / 112 page

AD9548

Rev. 0 | Page 58 of 112

I/O PROGRAMMING REGISTERS

The register map spans an address range from 0x0000 through

0x0E3F (0 to 3647, decimal). Each address provides access to 1

byte (eight bits) of data. Each individual register is identified by

its four-digit hexadecimal address (for example, Register 0A10).

In some cases, a group of addresses collectively define a register

(for example, the IRQ mask register consists of Register 0209,

In general, when a group of registers defines a control

parameter, the LSB of the value resides in the D0 position of the

to left, from the lowest register address to the highest register

address. For example, the default value of the incremental phase

lock offset step size register (Address 0314 to Address 0315) is

the 16-bit hexadecimal number, 0x03E8 (not 0xE803).

Note that the EEPROM storage sequence registers (Address

0E10 to Address 0E3F) are an exception to the above convention

(see the EEPROM Instructions section).

BUFFERED/ACTIVE REGISTERS

There are two broad categories of registers in the AD9548,

buffered and active (see Figure 65). Buffered registers are those

that can be written to directly from the serial port. They do not

need an I/O update to apply their contents to the internal device

functions. In contrast, active registers require an I/O update to

transfer data between the buffer registers and the internal

device functions. In operation, the user programs as many

buffer registers as desired and then issues an I/O update. The

I/O update occurs by writing to Register 0005, Bit 0 = 1 (or by

the external application of the necessary logic level to one of the

multifunction pins previously programmed as an I/O update

input). The contents of buffer registers connected directly to the

internal device functions affect those functions immediately.

The contents of buffer registers that connect to active registers

do not affect the internal device functions until the I/O update

event occurs.

An S or C in the Opt column of the register map identifies a

An S entry means that the I/O update signal to the active register is

synchronized with the serial port clock or with an input signal

driving one of the multifunction pins. On the other hand, a C

entry means that the I/O update signal to the active register is

synchronized with a clock signal derived from the internal

system clock (fS/32), as shown in Figure 65.

When reading back a register that has both buffered and active

contents, the user can use Register 0004, Bit 0 to select whether

to read back the buffer or active contents. Readback of the

active contents occurs when Register 0004, Bit 0 = 0, whereas

readback of the buffer contents occurs when Register 0004,

Bit 0 = 1. Note that a read-only active register requires an

I/O update before reading its contents.

FROM

MULTIFUNCTION

PIN LOGIC

SERIAL

CONTROL

PORT

fS/32

EDGE

DETECT

CS/SDA

SCLK/SCL

SDIO

SDO

Figure 65. Buffered and Active Registers

AUTOCLEAR REGISTERS

An A in the Opt column of the register map identifies an auto-

clear register. Typically, the active value for an autoclear register

takes effect following an I/O update. The bit is cleared by the

internal device logic upon completion of the prescribed action.

AD9548/PCBZ 数据表(PDF) 58 Page - Analog Devices

AD9548/PCBZ 数据表(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载