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521 数据表(PDF) 46 Page - Intel Corporation

部件名 521
功能描述  Pentium 4 Processors Supporting Hyper-Threading Technology
PDF  96 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

521 数据表(HTML) 46 Page - Intel Corporation

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Land Listing and Signal Descriptions
46
Datasheet
Table 4-1. Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction
A3#
L5
Source Synch
Input/Output
A4#
P6
Source Synch
Input/Output
A5#
M5
Source Synch
Input/Output
A6#
L4
Source Synch
Input/Output
A7#
M4
Source Synch
Input/Output
A8#
R4
Source Synch
Input/Output
A9#
T5
Source Synch
Input/Output
A10#
U6
Source Synch
Input/Output
A11#
T4
Source Synch
Input/Output
A12#
U5
Source Synch
Input/Output
A13#
U4
Source Synch
Input/Output
A14#
V5
Source Synch
Input/Output
A15#
V4
Source Synch
Input/Output
A16#
W5
Source Synch
Input/Output
A17#
AB6
Source Synch
Input/Output
A18#
W6
Source Synch
Input/Output
A19#
Y6
Source Synch
Input/Output
A20#
Y4
Source Synch
Input/Output
A20M#
K3
Asynch GTL+
Input
A21#
AA4
Source Synch
Input/Output
A22#
AD6
Source Synch
Input/Output
A23#
AA5
Source Synch
Input/Output
A24#
AB5
Source Synch
Input/Output
A25#
AC5
Source Synch
Input/Output
A26#
AB4
Source Synch
Input/Output
A27#
AF5
Source Synch
Input/Output
A28#
AF4
Source Synch
Input/Output
A29#
AG6
Source Synch
Input/Output
A30#
AG4
Source Synch
Input/Output
A31#
AG5
Source Synch
Input/Output
A32#
AH4
Source Synch
Input/Output
A33#
AH5
Source Synch
Input/Output
A34#
AJ5
Source Synch
Input/Output
A35#
AJ6
Source Synch
Input/Output
ADS#
D2
Common Clock Input/Output
ADSTB0#
R6
Source Synch
Input/Output
ADSTB1#
AD5
Source Synch
Input/Output
AP0#
U2
Common Clock Input/Output
AP1#
U3
Common Clock Input/Output
BCLK0
F28
Clock
Input
BCLK1
G28
Clock
Input
BINIT#
AD3
Common Clock Input/Output
BNR#
C2
Common Clock Input/Output
BOOTSELECT
Y1
Power/Other
Input
BPM0#
AJ2
Common Clock Input/Output
BPM1#
AJ1
Common Clock Input/Output
BPM2#
AD2
Common Clock Input/Output
BPM3#
AG2
Common Clock Input/Output
BPM4#
AF2
Common Clock Input/Output
BPM5#
AG3
Common Clock Input/Output
BPRI#
G8
Common Clock
Input
BR0#
F3
Common Clock Input/Output
BSEL0
G29
Power/Other
Output
BSEL1
H30
Power/Other
Output
BSEL2
G30
Power/Other
Output
COMP0
A13
Power/Other
Input
COMP1
T1
Power/Other
Input
D0#
B4
Source Synch
Input/Output
D1#
C5
Source Synch
Input/Output
D2#
A4
Source Synch
Input/Output
D3#
C6
Source Synch
Input/Output
D4#
A5
Source Synch
Input/Output
D5#
B6
Source Synch
Input/Output
D6#
B7
Source Synch
Input/Output
D7#
A7
Source Synch
Input/Output
D8#
A10
Source Synch
Input/Output
D9#
A11
Source Synch
Input/Output
D10#
B10
Source Synch
Input/Output
D11#
C11
Source Synch
Input/Output
D12#
D8
Source Synch
Input/Output
D13#
B12
Source Synch
Input/Output
D14#
C12
Source Synch
Input/Output
D15#
D11
Source Synch
Input/Output
D16#
G9
Source Synch
Input/Output
D17#
F8
Source Synch
Input/Output
D18#
F9
Source Synch
Input/Output
D19#
E9
Source Synch
Input/Output
D20#
D7
Source Synch
Input/Output
D21#
E10
Source Synch
Input/Output
D22#
D10
Source Synch
Input/Output
Table 4-1. Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction



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