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521 数据表(PDF) 60 Page - Intel Corporation

部件名 521
功能描述  Pentium 4 Processors Supporting Hyper-Threading Technology
PDF  96 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

521 数据表(HTML) 60 Page - Intel Corporation

Back Button 521 Datasheet HTML 56Page - Intel Corporation 521 Datasheet HTML 57Page - Intel Corporation 521 Datasheet HTML 58Page - Intel Corporation 521 Datasheet HTML 59Page - Intel Corporation 521 Datasheet HTML 60Page - Intel Corporation 521 Datasheet HTML 61Page - Intel Corporation 521 Datasheet HTML 62Page - Intel Corporation 521 Datasheet HTML 63Page - Intel Corporation 521 Datasheet HTML 64Page - Intel Corporation Next Button
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Land Listing and Signal Descriptions
60
Datasheet
P1
TESTHI11
Power/Other
Input
P2
SMI#
Asynch GTL+
Input
P3
INIT#
Asynch GTL+
Input
P4
VSS
Power/Other
P5
RESERVED
P6
A4#
Source Synch
Input/Output
P7
VSS
Power/Other
P8
VCC
Power/Other
P23
VSS
Power/Other
P24
VSS
Power/Other
P25
VSS
Power/Other
P26
VSS
Power/Other
P27
VSS
Power/Other
P28
VSS
Power/Other
P29
VSS
Power/Other
P30
VSS
Power/Other
R1
FC2
Power/Other
Input
R2
VSS
Power/Other
R3
FERR#/PBE#
Asynch GTL+
Output
R4
A8#
Source Synch
Input/Output
R5
VSS
Power/Other
R6
ADSTB0#
Source Synch
Input/Output
R7
VSS
Power/Other
R8
VCC
Power/Other
R23
VSS
Power/Other
R24
VSS
Power/Other
R25
VSS
Power/Other
R26
VSS
Power/Other
R27
VSS
Power/Other
R28
VSS
Power/Other
R29
VSS
Power/Other
R30
VSS
Power/Other
T1
COMP1
Power/Other
Input
T2
FC4
Power/Other
Input
T3
VSS
Power/Other
T4
A11#
Source Synch
Input/Output
T5
A9#
Source Synch
Input/Output
T6
VSS
Power/Other
T7
VSS
Power/Other
T8
VCC
Power/Other
T23
VCC
Power/Other
Table 4-2. Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
T24
VCC
Power/Other
T25
VCC
Power/Other
T26
VCC
Power/Other
T27
VCC
Power/Other
T28
VCC
Power/Other
T29
VCC
Power/Other
T30
VCC
Power/Other
U1
VSS
Power/Other
U2
AP0#
Common Clock
Input/Output
U3
AP1#
Common Clock
Input/Output
U4
A13#
Source Synch
Input/Output
U5
A12#
Source Synch
Input/Output
U6
A10#
Source Synch
Input/Output
U7
VSS
Power/Other
U8
VCC
Power/Other
U23
VCC
Power/Other
U24
VCC
Power/Other
U25
VCC
Power/Other
U26
VCC
Power/Other
U27
VCC
Power/Other
U28
VCC
Power/Other
U29
VCC
Power/Other
U30
VCC
Power/Other
V1
MSID1
Power/Other
Output
V2
LL_ID0
Power/Other
Output
V3
VSS
Power/Other
V4
A15#
Source Synch
Input/Output
V5
A14#
Source Synch
Input/Output
V6
VSS
Power/Other
V7
VSS
Power/Other
V8
VCC
Power/Other
V23
VSS
Power/Other
V24
VSS
Power/Other
V25
VSS
Power/Other
V26
VSS
Power/Other
V27
VSS
Power/Other
V28
VSS
Power/Other
V29
VSS
Power/Other
V30
VSS
Power/Other
W1
MSID0
Power/Other
Output
W2
TESTHI12
Power/Other
Input
Table 4-2. Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction



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