| 数据搜索系统,热门电子元器件搜索 |
|
SPEAR320 数据表(PDF) 52 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPEAR320 数据表(HTML) 52 Page - STMicroelectronics |
|
52 / 73 page ![]() Timing requirements SPEAr320 52/73 Doc ID 16755 Rev 5 7.3.3 DDR2 command timings Figure 8. DDR2 command waveforms Table 30. DDR2 write cycle timings Symbol Description Min Max Unit tDQSS Positive DQS latching edge to associated CK edge -0.5 0.5 ns tDS DQ & DQM output setup time relative to DQS 0 0.25tCK – 0.76 ns tDH DQ & DQM output hold time relative to DQS 0 0.25tCK – 0.84 ns Table 31. DDR2 command timings Symbol Description Min Max Unit tIS Address and control output setup time 0 0.5tCK – 0.5 ns tIH Address and control output hold time 0 0.5tCK – 0.59 ns tIS tIH CLK ADDRESS AND COMMANDS |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |