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SPEAR320 数据表(PDF) 53 Page - STMicroelectronics |
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SPEAR320 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 73 page ![]() SPEAr320 Timing requirements Doc ID 16755 Rev 5 53/73 7.4 CLCD timing characteristics The characterization timing is done considering an output load of 10 pF on all the outputs. The CLCD has a wide variety of configurations and setting and the parameters change accordingly. Figure 9 and Table 32 specify the clock to output delay. Figure 9. CLCD waveform Table 32. CLCD timings Symbol Description Min Max Unit tCK CLCP clock period 20.83 41.66 ns tD CLCP to CLCD output data delay 0.97 3.74 ns tCK tD CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER CLCP |
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