SPEAR320 datasheet(14/73 Pages) STMICROELECTRONICS

14 / 73 page

Architecture overview

SPEAr320

14/73

Doc ID 16755 Rev 5

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Up to 416 Mbits per second data rate using 8 bit parallel data lines (SD8 bit mode)

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Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity

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Designed to work with I/O cards, Read-only cards and Read/Write cards

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Error Correction Code (ECC) support for MMC4.2 cards

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Supports Read wait Control, Suspend/Resume operation

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Supports FIFO Overrun and Underrun condition by stopping SD clock

3.7

Flexible static memory controller (FSMC)

SPEAr320 provides a Flexible Static Memory Controller (FSMC) which interfaces to external

parallel NAND Flash memories.

Main features:

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8/16-bit wide data path

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FSMC performs only one access at a time and only one external device is accessed

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Supports little-endian and big-endian memory architectures

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AHB burst transfer handling to reduce access time to external devices

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Supplies an independent configuration for each memory bank

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Programmable timings to support a wide range of devices

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Programmable wait states (up to 31)

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Programmable bus turnaround cycles (up to 15)

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Programmable output enable and write enable delays (up to 15)

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Independent chip select control for each memory bank

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Shares the address bus and the data bus with all the external peripherals

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Only chips selects are unique for each peripheral

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External asynchronous wait control

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Boot memory bank configurable at reset using external control pins

3.8

Multichannel DMA controller

Within its basic subsystem, SPEAr320 provides a DMA controller (DMAC) able to service up

to 8 independent DMA channels for serial data transfers between single source and

destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and

peripheral-to-peripheral).

Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per

channel.

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