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SPEAR320 数据表(PDF) 57 Page - STMicroelectronics |
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SPEAR320 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 73 page ![]() SPEAr320 Timing requirements Doc ID 16755 Rev 5 57/73 7.7 EMI timing characteristics Figure 14. EMI read cycle waveforms with acknowledgement on EMI_WAIT# Note: The values of tSE, tENr, tDCS, tSCS are programmable via the EMI registers. Note: Values in the above table are referred to the common internal source clock which has a period of tHCLK = 6 ns. Figure 15. EMI write cycle waveforms with acknowledgement on EMI_WAIT# Note: The values of tSE, tENw, tDCS, tSCS are programmable via the EMI registers. EMI_A EMI_BYTEN EMI_D EMI_CSn# EMI_OE# Address Byte Enable Data tSE tSCS tENr tDCS EMI_WAIT# tCS->Wait tWAIT Table 37. EMI timings for read cycle with acknowledgement on WAIT# Symbol Min tCS->Wait tHCLK tWAIT 4*tHCLK EMI_A EMI_BYTEN EMI_D EMI_CSn# EMI_WE# Write Data Byte Enable Data tSE tSCS tENw tDCS EMI_WAIT# tCS->tWAIT tWAIT |
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