SPEAR320 datasheet(72/73 Pages) STMICROELECTRONICS

72 / 73 page

Revision history

SPEAr320

72/73

Doc ID 16755 Rev 5

05-Jul-2011

Removed PU from description of MRESET in Table 3: Master clock,

RTC, Reset and 3.3 V comparator pin descriptions

Updated figures and tables in:

– Section 6.7: Power up sequence

– Section 7.3: DDR2 timing characteristics

– Section 7.4: CLCD timing characteristics

– Section 7.5: I2C timing characteristics

– Section 7.6: FSMC timing characteristics

– Section 7.9: MII Ethernet MAC 10/100 Mbps timing characteristics

– Section 7.10: SMII Ethernet MAC timing characteristics

– Section 7.11: SMI - Serial memory interface timing characteristics

Added Section 7.7: EMI timing characteristics.

Added Section 7.8: SDIO timing characteristics.

Updated Table 52: 10-bit ADC characteristics.

Updated Table 54: Thermal resistance characteristics.

Added the Tck max value for CLCP clock period in Table 32: CLCD

timings.

Updated Figure 19: MII TX waveforms.

Replaced “43.2 k

Ω” by “43.2 Ω” in Section 4.1: Required external

components (USB_TX_RTUNE bullet).

Table 45: Timing requirements for SSP (all modes): replaced column

“Value” by columns “Min” and “Max”.

Replaced “clock phase = 1” by “clock phase = 0” at the figure caption

of Figure 25.

Section 4.1: Required external components: added new bullet

“DITH_VDD_2V5: Add a ferrite bead to ball M4”.

Added a footnote for VDD 2.5 at Table 18: Recommended operating

conditions.

Updated the footnote at Table 21: Low voltage TTL DC output

specification (3 V< VDD <3.6 V).

Added a note at the beginning of Chapter 7: Timing requirements

Added Section 7.1: External interrupt timing characteristics and

Section 7.2: Reset timing characteristics.

Replaced “Embedded/custom selector” by “RAS select register” in

Figure 3: Hierarchical multiplexing scheme and Table 11: PL_GPIO

multiplexing scheme.

Replaced “Embedded IPs” by “Alternate functions” in Figure 3:

Hierarchical multiplexing scheme.

Replaced the FSMC pins naming in Section 7.6: FSMC timing

characteristics, as follows:

– NFIO by FSMC_Dx (where x=0 to 15)

– NF_CE by FSMC_CSx (where x= 0 to 3)

– NF_ALE by FSMC_ADDR_LE

–NF_WE by FSMC_WE

– NF_RE by FSMC_RE

– NF_CLE by FSMC_CMD_LE

Table 55.

Document revision history (continued)

Date

Revision

Changes

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