SPEAR320 datasheet(8/73 Pages) STMICROELECTRONICS

8 / 73 page

Description

SPEAr320

8/73

Doc ID 16755 Rev 5

Description

The SPEAr320 is a member of the SPEAr family of embedded MPUs, optimized for

industrial automation and consumer applications. It is based on the powerful ARM926EJ-S

processor (up to 333 MHz), widely used in applications where high computation

performance is required.

In addition, SPEAr320 has an MMU that allows virtual memory management - making the

system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of

instruction cache, JTAG and ETM (Embedded Trace Macrocell

™) for debug operations.

A full set of peripherals allows the system to be used in many applications, some typical

applications being factory automation, printer and consumer applications.

Figure 1.

Functional block diagram

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USB Device 2.0 +Phy

IrDA

USB

Host

2.0

Phy

2x CAN

3x SSP

2x Ethernet 10/100

(SMII/MII interface)

Mobile DDR/DDR2

memory controller

32 KBytes BootRom

8 KBytes SRAM

FSMC NAND

Flash interface

JTAG/trace

ARM926EJ-S

@333 MHz

System controller

Interrupt controller

Watchdog

RTC

PLLs

ICache

DCache

MMU

= Functions with shared I/Os depending on the device configuration.

C3 Crypto

accelerator

MultiChannel DMA controller

JPEG CODEC

accelerator

EMI NOR Flash/

FPGA interface

Hub

Up to 102 GPIOs

2x I2C master/slave

LCD controller

1024*768

Std parallel port

ADC

6x general purpose timer

3x UART

IrDA

4x PWM timer

Serial Flash interface

SDIO/MMC card interface

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