SPEAR320 datasheet(20/73 Pages) STMICROELECTRONICS

20 / 73 page

Architecture overview

SPEAr320

20/73

Doc ID 16755 Rev 5

3.15

Parallel port

Main features:

●

Slave mode device interface for standard parallel port host

●

Supports unidirectional 8-bit data transfer from host to slave

●

Supports 9th bit for parity/data/command etc.

●

Maskable interrupts for data, device reset, auto line feed

●

APB input clock frequency required is 83 MHz for acknowledgement timings

3.16

Synchronous serial ports (SSP)

SPEAr320 provides three synchronous serial ports (SSP) that offer a master or slave

interface to enable synchronous serial communication with slave or master peripherals

Main features:

●

Master or slave operation.

●

Programmable clock bit rate and prescale.

●

Separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations

deep.

●

Programmable choice of interface operation:

–

SPI (Motorola)

–

Microwire (National Semiconductor)

–

TI synchronous serial.

●

Programmable data frame size from 4 to 16-bits.

●

Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts.

●

Internal loopback test mode available.

●

DMA interface

3.17

I2C

The SPEAr320 has 2 I2C interfaces:

Main features:

●

Compliance to the I2C bus specification (Philips)

●

Supports three modes:

–

Standard (100 kbps)

–

Fast (400 kbps)

–

High-speed

●

Clock synchronization

●

Master and slave mode configuration possible

●

Multi-master mode (bus arbitration)

●

7-bit or 10-bit addressing

●

7-bit or 10-bit combined format transfers

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