SPEAR320 datasheet(19/73 Pages) STMICROELECTRONICS

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SPEAr320

Architecture overview

Doc ID 16755 Rev 5

19/73

3.13

CLCD controller

SPEAr320 has a color liquid crystal display controller (CLCDC) that provides all the

necessary control signals to interface directly to a variety of color and monochrome LCD

panels.

Main features:

●

Resolution programmable up to 1024 x 768

●

16-bpp true-color non-palletized, for color STN and TFT

●

24-bpp true-color non-palletized, for color TFT

●

Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-

bit interfaces

●

Supports single and dual-panel color and monochrome STN displays

●

Supports thin film transistor (TFT) color displays

●

15 gray-level mono, 3375 color STN, and 32 K color TFT support

●

1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN

●

1, 2, 4 or 8-bpp palletized color displays for color STN and TFT

●

Programmable timing for different display panels

●

256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line

and pixel clock signals

●

AC bias signal for STN and data enable signal for TFT panels patented gray scale

algorithm

●

Supports little and big-endian

3.14

GPIOs

A maximum of 102 GPIOs (PL_GPIOs) are available when part of the embedded IPs are not

needed (see Section 4.3: Shared I/O pins (PL_GPIOs)).

Within its basic subsystem, SPEAr320 provides a base General Purpose Input/Output

(GPIO) block (basGPIO). The base GPIO block provides 6 programmable inputs or outputs.

Each input/output can be controlled in two distinct modes:

●

Software mode, through an APB interface.

●

Hardware mode, through a hardware control interface.

Main features of the base GPIO block are:

●

Six individually programmable input/output pins (default to input at reset)

●

An APB slave acting as control interface in "software mode"

●

Programmable interrupt generation capability on any number of pins.

●

Hardware control capability of GPIO lines for different system configurations.

●

Bit masking in both read and write operation through address lines.

Other GPIO blocks are present in the reconfigurable array subsystem.

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