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SPEAR320 数据表(PDF) 58 Page - STMicroelectronics |
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SPEAR320 数据表(HTML) 58 Page - STMicroelectronics |
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58 / 73 page ![]() Timing requirements SPEAr320 58/73 Doc ID 16755 Rev 5 Note: Values in the above table are referred to the common internal source clock which has a period of tHCLK = 6 ns. Figure 16. EMI read cycle waveforms without acknowledgement on EMI_WAIT# Note: The values of tSE, tENr, tDCS, tSCS are programmable via the EMI registers. Figure 17. EMI write cycle waveforms without acknowledgement on EMI_WAIT# Note: The values of tSE, tENw, tDCS, tSCS are programmable via the EMI registers. Table 38. EMI timings for write cycle with acknowledgement on WAIT# Symbol Min tCS->Wait tHCLK tWAIT 4*tHCLK EMI_A EMI_BYTEN EMI_D EMI_CSn# EMI_OE# Address Byte Enable Data tSE tSCS tENr tDCS EMI_A EMI_BYTEN EMI_D EMI_CSn# EMI_WE# Write Data Byte Enable Data tSE tSCS tENw tDCS |
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