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SPEAR320 数据表(PDF) 55 Page - STMicroelectronics |
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SPEAR320 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 73 page ![]() SPEAr320 Timing requirements Doc ID 16755 Rev 5 55/73 Note: The timings shown in Figure 10 depend on the programmed value of tSCLHigh and tSCLLow, so the values present in the three tables here above have been calculated using the minimum programmable values of : ● IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode); ● IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode); ● IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed mode). These minimum values depend on the AHB clock frequency, which is 166 MHz. 7.6 FSMC timing characteristics The characterization timing is done using primetime considering an output load of 3 pF on the data, 15 pF on FSMC_CSx, FSMC_RE and FSMC_WE and 10 pF on FSMC_ADDR_LE and FSMC_CMD_LE. 7.6.1 NAND Flash configuration Figure 11. Output command signal waveforms for NAND Flash Table 35. Timing characteristics for I2C in standard speed mode Parameter Min Unit tSU-STA 4723.6 ns tHD-STA 3991.9 tSU-DAT 4676.1 tHD-DAT 0.8 tSU-STO 4027.7 tHD-STO 4742.2 FSMC_CSx FSMC_WE FSMC_Dx Command tCLE tWE tIO FSMC_CMD_LE |
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