SPEAR320 datasheet(12/73 Pages) STMICROELECTRONICS

12 / 73 page

Architecture overview

SPEAr320

12/73

Doc ID 16755 Rev 5

The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction

cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which

makes it fully compliant with Linux and VxWorks operating systems.

It also includes an embedded trace module (ETM Medium+) for real-time CPU activity

tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed

trace mode, with normal or half-rate clock.

3.2

Embedded memory units

●

32 Kbytes of BootROM

●

8 Kbytes of SRAM

3.2.1

BootROM

BootROM is small firmware program that is executed just after the SPEAr320 exits from

reset.

It supports the following boot modes:

●

Boot from NOR serial Flash

●

Boot from NAND Flash

●

Boot from NOR parallel Flash

●

Boot / Upgrade from USB

The first three modes support different ways of booting the application software, they require

a second-level boot software (Xloader) to be located in Flash.

USB boot mode can be used for software maintenance or upgrade, if booting from any of

the Flash memories is not possible.

The BootROM selects the boot mode from the boot pin settings (see Section 4.3.4: Boot

pins). A setting is available to allow the BootROM to be bypassed.

3.3

Mobile DDR/DDR2 memory controller

SPEAr320 integrates a high performance multi-channel memory controller able to support

low power Mobile DDR and DDR2 double data rate memory devices. The multi-port

architecture ensures memory is shared efficiently among different high-bandwidth client

modules.

It has 6 internal ports. One of them is reserved for register access during the controller

initialization while the other five are used to access the external memory.

It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to

maximize the data valid windows at different frequencies.

3.4

Serial memory interface

SPEAr320 provides a serial memory interface (SMI), acting as an AHB slave interface (32-

, 16- or 8-bit) to SPI-compatible off-chip memories.

These serial memories can be used either as data storage or for code execution.

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