WM8904ECSSLASHR datasheet(106/188 Pages) WOLFSON

106 / 188 page

WM8904

Pre-Production

PP, Rev 3.3, September 2012

106

OPCLK CONTROL

A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled

by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.

This output of this clock is also dependent upon the GPIO register settings described under “General

Purpose Input/Output (GPIO)”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22 (16h)

Clock Rates 2

OPCLK_ENA

GPIO Clock Output Enable

0 = disabled

1 = enabled

R26 (1Ah)

Audio

Interface 2

11:8

OPCLK_DIV [3:0]

0000

GPIO Output Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16

1001 to 1111 = Reserved

Table 64 OPCLK Control

TOCLK CONTROL

A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-

bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,

and its frequency is controlled by TOCLK_RATE and TOCLK_RATE_X4, as described in Table 65.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22 (16h)

Clock Rates 2

TOCLK_RATE

TOCLK Rate Divider (/2)

0 = f / 2

1 = f / 1

TOCLK_ENA

Zero Cross timeout enable

0 = Disabled

1 = Enabled

R20 (14h)

Clock Rates 0

TOCLK_RATE_

DIV16

TOCLK Rate Divider (/16)

0 = f / 1

1 = f / 16

TOCLK_RATE_

TOCLK Rate Multiplier

0 = f x 1

1 = f x 4

Table 65 TOCLK Control

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