WM8904ECSSLASHR datasheet(107/188 Pages) WOLFSON

107 / 188 page

Pre-Production

WM8904

PP, Rev 3.3, September 2012

107

A list of possible TOCLK rates is provided in Table 66.

TOCLK_RATE

TOCLK_RATE_X4

TOCLK_RATE_DIV16

TOCLK

FREQ (Hz)

PERIOD

(ms)

1000

500

250

125

62.5

31.25

15.625

7.8125

128

Table 66 TOCLK Rates

ADC / DAC OPERATION AT 88.2K / 96K

The WM8904 supports ADC or DAC operation at 88.2kHz and 96kHz sample rates. This section

details specific conditions applicable to these operating modes. Note that simultaneous ADC and

DAC operation at 88.2kHz or 96kHz is not possible.

For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are

detailed in Table 67. DAC operation at these sample rates is achieved by setting the SAMPLE_RATE

field to half the required sample rate (eg. select 48kHz for 96kHz mode).

For DAC operation at 88.2kHz or 96kHz sample rates, the ADCs must both be disabled (ADCL_ENA

= 0 and ADCR_ENA = 0). Also, the DAC_OSR128 register must be set to 0. ReTune

TM Mobile can

not be used during 88.2kHz or 96kHz operation, so EQ_ENA must be set to 0.

The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the

“Signal Timing Requirements” section.

SAMPLE RATE

CLOCKING RATIO

88.2kHz

SAMPLE_RATE = 101

CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)

BCLK_DIV = 00010

LRCLK_RATE = 040h

SYSCLK = 128 x fs

96kHz

SAMPLE_RATE = 101

CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)

BCLK_DIV = 00010

LRCLK_RATE = 040h

SYSCLK = 128 x fs

Table 67 DAC Operation at 88.2kHz and 96kHz Sample Rates

For ADC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are

detailed in Table 68.

ADC operation at these sample rates is achieved by setting the SAMPLE_RATE field to half the

required sample rate (eg. select 48kHz for 96kHz mode). For ADC operation at 88.2kHz or 96kHz

sample rates, the DACs must both be disabled (DACL_ENA = 0 and DACR_ENA = 0). Note that

ADC_OSR128, ADC_128_OSR_TST_MODE, and ADC_BIASX1P5 must be configured according to

Table 68.

The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the

“Signal Timing Requirements” section.

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