WM8904ECSSLASHR datasheet(111/188 Pages) WOLFSON

111 / 188 page

Pre-Production

WM8904

PP, Rev 3.3, September 2012

111

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

6:4

FLL_CTRL_RAT

E [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended

value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

110 = FVCO / 7

111 = FVCO / 8

Recommended that these are not

changed from default.

2:0

FLL_FRATIO

[2:0]

111

FVCO clock divider

000 = divide by 1

001 = divide by 2

010 = divide by 4

011 = divide by 8

1XX = divide by 16

000 recommended for FREF > 1MHz

100 recommended for FREF < 64kHz

R118 (76h)

FLL Control 3

15:0

FLL_K [15:0]

0000h

Fractional multiply for FREF

(MSB = 0.5)

R119 (77h)

FLL Control 4

14:5

FLL_N [9:0]

177h

Integer multiply for FREF

(LSB = 1)

3:0

FLL_GAIN [3:0]

Gain applied to error

0000 = x 1 (Recommended value)

0001 = x 2

0010 = x 4

0011 = x 8

0100 = x 16

0101 = x 32

0110 = x 64

0111 = x 128

1000 = x 256

Recommended that these are not

changed from default.

R120 (78h)

FLL Control 5

4:3

FLL_CLK_REF_

DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must

be divided down to <=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

WM8904ECS/R 数据表(PDF) 111 Page - Wolfson Microelectronics plc

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