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WM8904ECS/R 数据表(PDF) 169 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 169 Page - Wolfson Microelectronics plc |
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169 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 169 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R116 (74h) FLL Control 1 2 FLL_FRACN_E NA 0 FLL Fractional enable 0 = Integer Mode 1 = Fractional Mode Fractional Mode (FLL_FRACN_ENA=1) is recommended in all cases Frequency Locked Loop (FLL) 1 FLL_OSC_ENA 0 FLL Oscillator enable 0 = Disabled 1 = Enabled FLL_OSC_ENA must be enabled before enabling FLL_ENA. Note that this field is required for free-running FLL modes only. Frequency Locked Loop (FLL) 0 FLL_ENA 0 FLL Enable 0 = Disabled 1 = Enabled FLL_OSC_ENA must be enabled before enabling FLL_ENA. Frequency Locked Loop (FLL) Register 74h FLL Control 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R117 (75h) FLL Control 2 13:8 FLL_OUTDIV [5:0] 00_0000 FLL FOUT clock divider 00_0000 = Reserved 00_0001 = Reserved 00_0010 = Reserved 00_0011 = 4 00_0100 = 5 00_0101 = 6 … 11_1110 = 63 11_1111 = 64 (FOUT = FVCO / FLL_OUTDIV) Frequency Locked Loop (FLL) 6:4 FLL_CTRL_RAT E [2:0] 000 Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that these are not changed from default. Frequency Locked Loop (FLL) 2:0 FLL_FRATIO [2:0] 111 FVCO clock divider 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 Frequency Locked Loop (FLL) |
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