S12OSCV2D datasheet(107/126 Pages) FREESCALE

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MC9S12DJ64 Device User Guide — V01.17

107

A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)

is also the system clock source in self clock mode.

A.5.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

Figure A-2 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical

values for K1, f1 and ich from Table A-16.

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used

for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

NOTES:

1. Depending on the crystal a damping series resistor might be necessary

2. fosc = 4MHz, C = 22pF.

3. Maximum value is for extreme cases using high Q, low frequency crystals

4. Only valid if Pierce oscillator/external clock mode is selected

fosc

refdv+1

fref

Phase

Detector

VCO

synr+1

fvco

Loop Divider

KΦ

∆

fcmp

VDDPLL

XFC Pin

1 e

vco

–

()

⋅

-----------------------

⋅

100

–

()

100

–

------------------------

⋅

= -90.48MHz/V

S12OSCV2D 数据表(PDF) 107 Page - Freescale Semiconductor, Inc

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