S12OSCV2D datasheet(108/126 Pages) FREESCALE

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MC9S12DJ64 Device User Guide — V01.17

108

The phase detector relationship is given by:

ich is the current in tracking mode.

The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,

typical values are 50.

ζ = 0.9 ensures a good transient response.

And finally the frequency relationship is defined as

With the above values the resistance can be calculated. The example is shown for a loop bandwidth

fC=10kHz:

The capacitance Cs can now be calculated as:

The capacitance Cp should be chosen in the range of:

A.5.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the

deviation from the reference clock fref is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.

Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock

jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.

KΦ

–

⋅

= 316.7Hz/

Ω

ζ f

ref

⋅⋅

πζ





⋅

------------------------------------------

------

ref

410

⋅

--------------

ζ 0.9

()

;

→

fC < 25kHz

VCO

ref

-------------

synr

()

⋅

= 50

π nf

⋅⋅ ⋅

KΦ

-----------------------------

=2*

π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ

⋅

π f

C R

⋅⋅

----------------------

0.516

C R

⋅

---------------

ζ 0.9

()

;

≈

= 5.19nF =~ 4.7nF

s 20

⁄

s 10

⁄

≤≤

Cp = 470pF

S12OSCV2D 数据表(PDF) 108 Page - Freescale Semiconductor, Inc

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