S12OSCV2D datasheet(110/126 Pages) FREESCALE

110 / 126 page

MC9S12DJ64 Device User Guide — V01.17

110

This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the

effect of the jitter to a large extent.

Table A-16 PLL Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

P Self Clock Mode frequency

fSCM

5.5

MHz

D VCO locking range

fVCO

MHz

Lock Detector transition from Acquisition to Tracking

mode

|∆

trk|

NOTES:

1. % deviation from target frequency

D Lock Detection

|∆

Lock|

1.5

D Un-Lock Detection

|∆

unl|

0.5

2.5

Lock Detector transition from Tracking to Acquisition

mode

|∆

unt|

7C PLLON Total Stabilization delay (Auto Mode) 2

2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =

10K

Ω.

tstab

0.5

8D PLLON Acquisition mode stabilization delay 2

tacq

0.3

9D PLLON Tracking mode stabilization delay 2

tal

0.2

D Fitting parameter VCO loop gain

-100

MHz/V

D Fitting parameter VCO loop frequency

MHz

D Charge pump current acquisition mode

| ich |

38.5

µA

D Charge pump current tracking mode

| ich |

3.5

µA

C Jitter ﬁt parameter 12

1.1

C Jitter ﬁt parameter 22

0.13

S12OSCV2D 数据表(PDF) 110 Page - Freescale Semiconductor, Inc

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