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ADRF6850BCPZ-R7 数据表(PDF) 3 Page - Analog Devices |
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ADRF6850BCPZ-R7 数据表(HTML) 3 Page - Analog Devices |
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3 / 36 page  ADRF6850 Rev. 0 | Page 3 of 36 SPECIFICATIONS VCC = 3.3 V; ambient temperature (TA) = 25°C; ZS = 50 Ω; ZL = 100 Ω differential; PLL loop bandwidth = 50 kHz; REFIN = 13.5 MHz; PFD = 27 MHz; baseband frequency = 20 MHz, narrow-band mode, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RF INPUT RFI, RFI, VGAIN pins Operating Frequency Range 100 1000 MHz Input P1dB 0 dB gain +12 dBm 60 dB gain −48 dBm Input IP3 0 dB gain +22.5 dBm 60 dB gain −38 dBm Input IP2 0 dB gain, single-ended input +40 dBm 60 dB gain, single-ended input −20 dBm Noise Figure (NF) 0 dB gain 49 dB <39 dB gain NF rises 1:1 as gain in dB falls >39 dB gain 11 dB Maximum Gain Z S = 50 Ω single-ended, ZL = 100 Ω differential 60 dB Minimum Gain Z S = 50 Ω single-ended, ZL = 100 Ω differential 0 dB Gain Conformance Error1 V GAIN from 200 mV to 1.3 V 0.5 dB Gain Slope 25 mV/dB VGAIN Input Impedance 20 kΩ Return Loss Relative to Z S = 50 Ω, 100 MHz to 1 GHz 15 dB REFERENCE CHARACTERISTICS REFIN pin Input Frequency With R divide-by-2 divider enabled 10 300 MHz With R divide-by-2 divider disabled 10 165 MHz REFIN Input Sensitivity 0.4 V CC V p-p REFIN Input Capacitance 10 pF REFIN Input Current ±100 µA CHARGE PUMP CP and RSET pins I CP Sink/Source Programmable High Value With R SET = 4.7 kΩ 5 mA Low Value 312.5 µA Absolute Accuracy With R SET = 4.7 kΩ 2.5 % VCO Gain K VCO 15 MHz/V SYNTHESIZER SPECIFICATIONS Loop bandwidth = 50 kHz Frequency Increment 1 Hz Phase Frequency Detector 10 30 MHz Spurs Integer boundary < loop bandwidth −55 dBc >10 MHz offset from carrier −70 dBc Phase Noise LO frequency = 1000 MHz @ 10 Hz offset −75 dBc/Hz @ 100 Hz offset −80 dBc/Hz @ 1 kHz offset −90 dBc/Hz @ 10 kHz offset −98 dBc/Hz @ 100 kHz offset −110 dBc/Hz @ 1 MHz offset −136 dBc/Hz >10 MHz offset −149 dBc/Hz Integrated Phase Noise 1 kHz to 8 MHz integration bandwidth 0.26 °rms |
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