ADRF6850

Rev. 0 | Page 8 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

VCC1

2

IBB

3

IBB

4

QBB

5

QBB

6

GND

7

VOCM

8

GND

9

RSET

10

LF3

11

CP

12

LF2

13

VCC2

14

VCC3

35 CCOMP3

36 VCC7

37 GND

38 VTUNE

39 MUXOUT

40 LDET

41 GND

42 VCC8

34 CCOMP2

33 CCOMP1

32 GND

31 VCC6

30 CLK/SCL

29 SDI/SDA

TOP VIEW

(Not to Scale)

ADRF6850

NOTES

1. CONNECT EXPOSED PAD TO GROUND PLANE VIA

A LOW IMPEDANCE PATH.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 13, 14, 15, 16,

31, 36, 42, 49

VCC1 to VCC9

Positive Power Supplies. Apply a 3.3 V power supply to all VCCx pins. Decouple each pin with a power

supply decoupling capacitor.

6, 8, 19, 20, 21,

24, 32, 37, 41,

44, 45, 46, 47,

48, 50, 52, 54, 56

GND

Analog Ground. Connect to a low impedance ground plane.

2, 3, 4, 5

IBB, IBB, QBB,

QBB

Differential In-Phase and Quadrature Baseband Outputs. These low impedance outputs can drive

2.5 V p-p into 100 Ω differential loads.

7

VOCM

Baseband Common-Mode Voltage Input. When ac coupling the baseband output pins, ground

VOCM. There is an option to apply an external voltage, which may be relevant when dc coupling the

baseband output pins. Note that Register CR29, Bit 6 must be set accordingly.

33

CCOMP1

Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.

34

CCOMP2

Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.

35

CCOMP3

Internal Compensation Node. This pin must be decoupled to ground with a 100 nF capacitor.

38

VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering

the CP output voltage.

9

RSET

Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum

charge pump output current. The relationship between I

SET

CPmax

R

I

5

.

23

=

where R

11

CP

Charge Pump Output. When enabled, this provides ±I

drives the internal VCO.

27

CS

Chip Select. CMOS input. When CS is high, the data stored in the shift registers is loaded into one of

low, the slave address is 0x58.

29

SDI/SDA

bidirectional port.

30

CLK/SCL

This input is a high impedance CMOS input.

28

SDO

Serial Data Output for SPI Port. Register states can be read back on the SDO data output line in an

8-bit word.

17

REFIN

Reference Input. AC couple this high impedance CMOS input.

18

REFIN

Reference Input Bar. Ground this pin.