ADRF6850

Rev. 0 | Page 9 of 36

Pin No.

Mnemonic

Description

51, 55

RFI, RFI

RF Inputs. 50 Ω internally biased RF inputs. For single-ended operation, RFI must be ac-coupled to

the source, and RFI must be ac-coupled to the ground plane.

53

RFCM

RF Input Common Mode. Connect to RFI when driving the input in single-ended mode. When driving

the input differentially using a balun, connect this pin to the common terminal of the output coil of

the balun. Decouple RFCM to the ground plane.

25, 26

LOMON,

LOMON

Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency

(1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately.

These open-collector outputs must be terminated with external resistors to VCCx. These outputs can

be disabled through serial port programming and should be connected to VCCx if not used.

10, 12

LF3/LF2

Extra Loop Filter Pins for Fastlock. Use these pins to reduce lock time.

40

LDET

Lock Detect. This pin provides an active high output when the PLL frequency is locked. The lock

detect timing is controlled by Register CR14 (Bit 7) and Register CR23 (Bit 3).

39

MUXOUT

Muxout. This output is a test output for diagnostic use only. Allow this pin to remain open circuit.

22, 23

TESTLO, TESTLO

Differential Test Inputs. For internal use only. These pins should be grounded.

43

VGAIN

VGA Gain Input. Drive this pin by a voltage in the range from 0 V to 1.5 V. This voltage controls the

gain of the VGA. A 0 V input sets the VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to

+60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set to 0. If the VGA gain mode polarity bit is

set to 1, a 0 V input sets the VGA gain to +60 dB, whereas a 1.5 V input sets the VGA gain to 0 dB.

EP

Exposed Paddle. Connect the exposed pad to the ground plane via a low impedance path.