ADRF6850BCPZ-R7 datasheet(24/36 Pages) AD

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ADRF6850

Rev. 0 | Page 24 of 36

PROGRAM MODES

The ADRF6850 has 34 8-bit registers to allow program control

of a number of functions. Only 31 of these registers are writeable.

Either an SPI or an I2C interface can be used to program the

Figure 61 to Figure 67. The registers are documented in Table 8

to Table 27.

Several settings in the ADRF6850 are double buffered. These

settings include the FRAC value, the INT value, the RFDIV

value, the 5-bit R-divider value, the reference doubler, the R ÷2

divider, and the charge pump current setting. This means that

two events must occur before the part uses a new value for any

of the double buffered settings. First, the new value is latched

into the device by writing to the appropriate register. Next, a new

write must be performed on Register CR0. When Register CR0 is

written, a new PLL acquisition occurs.

For example, updating the fractional value involves a write to

and Register CR1 and, finally, Register CR0. The new acquisition

begins after the write to Register CR0. Double buffering ensures

that the bits written to do not take effect until after the write to

12-Bit Integer Value

of the feedback division factor (N); see Equation 5 for details.

The INT value is a 12-bit number whose MSBs are programmed

through Register CR7, Bits[3:0]. The LSBs are programmed

through Register CR6, Bits[7:0]. The LO frequency setting is

described by Equation 2. An alternative to this equation is pro-

vided by Equation 4, which details how to set the N-divider

value. Note that these registers are double buffered.

25-Bit Fractional Value

of the feedback division factor (N); see Equation 5 for details. The

FRAC value is a 25-bit number whose MSB is programmed

through Register CR3, Bit 0. The LSB is programmed through

Equation 2. Again, an alternative to this equation is described

by Equation 4, which details how to set the N-divider value.

Note that these registers are double buffered.

RFDIV Value

The RFDIV value is dependent on the value of the LO frequency.

The RFDIV value can be selected from the list in Table 6. Apply

the selected RFDIV value to Equation 4, together with the LO

frequency and PFD frequency values, to calculate the correct N-

divider value.

Reference Input Path

The reference input path consists of a reference doubler, a 5-bit

frequency divider, and a divide-by-2 function (see Figure 54).

The doubler is programmed through Register CR10, Bit 5. The

5-bit divider is enabled by programming Register CR5, Bit 4;

and the division ratio is programmed through Register CR10,

Bits[4:0]. The R ÷2 divider is programmed through Register CR10,

Bit 6. Note that these registers are double buffered.

Charge Pump Current

With an RSET value of 4.7 kΩ, the maximum charge pump

current is 5 mA. The following equation applies:

ICP max = 23.5/RSET

(6)

The charge pump current has 16 settings from 325 μA to 5 mA.

Power-Down/Power-Up Control Bits

The four programmable power-up and power-down control bits

are as follows:



including the VCO. This bit is normally set to a default

value of 0 to power up the PLL.



LOMON and LOMON. The default is 0 when the monitor

outputs are powered down. Setting this bit to 1 powers up

the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm,

or −24 dBm, as controlled by Register CR27, Bits[1:0].



power. The default is 0, which powers down the demodulator.

Write a 1 to this bit to power up the demodulator.



must be set to a 1 to power up the VGA.

Lock Detect (LDET)

Lock detect is enabled by setting Register CR23, Bit 4, to 1.

sets the number of up/down pulses generated by the PFD before

lock detect is declared by the LDET pin returning high. The

options are 2048 pulses, 3072 pulses, and 4096 pulses.

The default setting is 3072 pulses, which is selected by program-

ming Register CR23, Bit 3, to 0, and Register CR14, Bit 7, to 0. A

more aggressive setting of 2048 is selected when Register CR23,

Bit 3, is set to 1 and Register CR14, Bit 7, is set to 0. This improves

the lock detect time by 50 μs (for a PFD frequency of 27 MHz).

Note, however, that it does not affect the acquisition time to an

error frequency of 1 kHz. A setting of 4096 pulses is selected

when Register CR14, Bit 7, is set to 1. For best operation, set

pulses to a coarse or low precision setting.

Baseband VOCM Reference

for the baseband outputs is internal or external. When the base-

band outputs are ac-coupled, then the internal reference must

be selected by setting Register CR29, Bit 6, to 1, and by

grounding Pin 7, VOCM.

When the baseband outputs are dc-coupled, it is likely that an

external bias is needed unless the internal dc bias provided is

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