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ADRF6850BCPZ-R7 数据表(PDF) 29 Page - Analog Devices

部件名 ADRF6850BCPZ-R7
功能描述  100 MHz to 1000 MHz Integrated Broadband Receiver
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6850BCPZ-R7 数据表(HTML) 29 Page - Analog Devices

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ADRF6850
Rev. 0 | Page 29 of 36
Table 21. Register CR24 (Address 0x18), Autocalibration
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Disable autocalibration
0 = enable autocalibration (default)
1 = disable autocalibration
Table 22. Register CR25 (Address 0x19), Autocalibration
Timer
Bit
Description
[7:0]
Autocalibration timer
Table 23. Register CR27 (Address 0x1B), LO Monitor Output
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Power-up monitor output
0 = power down (default)
1 = power up
[1:0]
Monitor output power into 50 Ω
00 = −24 dBm (default)
01 = −18 dBm
10 = −12 dBm
11 = −6 dBm
Table 24. Register CR28 (Address 0x1C), LO Selection
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved; set to 1
[2:0]
RFDIV
000 = divide by 1; LO = 500 MHz to 1000 MHz
001 = divide by 2; LO = 250 MHz to 500 MHz
010 = divide by 4; LO = 125 MHz to 250 MHz
011 = divide by 8; LO = 100 MHz to 125 MHz
Table 25. Register CR29 (Address 0x1D), Demodulator
Power and Filter Selection
Bit
Description
7
Reserved
6
Internal baseband (V
OCM) select
0 = select external baseband (V
OCM) reference
1 = select internal baseband (V
OCM) reference
[5:4]
Narrow-band filter cut off
00 = 50 MHz
01 = 43 MHz
10 = 37 MHz
11 = 30 MHz
3
Baseband wideband/narrow-band modes
0 = narrow-band mode
1 = wideband mode
2
Reserved; set to 0
1
Reserved; set to 0
0
Power-up demodulator
0 = power down (default)
1 = power up
Table 26. Register CR30 (Address 0x1E), VGA
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
VGA gain mode polarity
0 = positive gain slope
1 = negative gain slope
1
Reserved
0
Power-up VGA
0 = power down
1 = power up
Table 27. Register CR33 (Address 0x21), Revision Code1
Bit
Description
7
Revision code
6
Revision code
5
Revision code
4
Revision code
3
Revision code
2
Revision code
1
Revision code
0
Revision code
1 Read-only register.



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