ADRF6850BCPZ-R7 datasheet(20/36 Pages) AD

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ADRF6850

Rev. 0 | Page 20 of 36

The VCO displays a variation of KVCO as VTUNE varies within

the band and from band to band. Figure 60 shows how the

KVCO varies across the fundamental LO frequency range from

500 MHz to 1000 MHz. Note that KVCO is shown at the LO

frequency rather than at the VCO frequency. Figure 60 is useful

when calculating the loop filter bandwidth and individual loop

filter components using ADISimPLL™. ADISimPLL is an

Analog Devices, Inc., simulator that aids in PLL design,

particularly with respect to the loop filter. It reports parameters

such as phase noise, integrated phase noise, acquisition time,

and so forth for a particular set of input conditions.

ADISimPLL can be downloaded from www.analog.com.

500

550

600

650

700

750

800

850

900

950

1000

LO FREQUENCY (MHz)

Figure 60. KVCO vs. LO Frequency

Programming the Correct LO Frequency

There are two steps to programming the correct LO frequency.

The user can calculate the N-divider ratio that is required in the

PLL and the RFDIV value based on the required LO frequency

and PFD frequency.

1. Calculate the value of RFDIV, which is used to program

(Table 6). See also Table 24.

Table 6. RFDIV Lookup Table

LO Frequency (MHz)

RFDIV = Register CR28[2:0]

500 to 1000

000 = divide-by-1

250 to 500

001 = divide-by-2

125 to 250

010 = divide-by-4

100 to 125

011 = divide-by-8

2. Using the following equation, calculate the value of the

N-divider:

N = (2RFDIV × 2 × LO)/(fPFD)

(4)

where:

N is the N-divider value.

RFDIV is the setting in Register CR28, Bits[2:0].

LO is the local oscillator frequency.

fPFD is the PFD frequency.

This equation is a different representation of Equation 2.

Example to Program the Correct LO Frequency

Assume that the PFD frequency is 27 MHz and the required LO

frequency is 330 MHz.

Step 1. From Table 6, 2RFDIV = 2.

Step 2. N = (2 × 2 × 330E+6)/(27E+6) = 48.88888889.

The N-divider value is composed of integer (INT) and

fractional (FRAC) components according to the following

equation:

N = INT + FRAC/225

(5)

INT = 48 and FRAC = 29,826,162.

The appropriate registers must then be programmed according to

the register map, ensuring that Register CR0 is the last register

to be programmed because this write starts a new PLL acquisi-

tion cycle.

QUADRATURE DEMODULATOR

The quadrature demodulator can be powered up by Register CR29,

Bit 0. It has an output filter with narrow-band and wideband

modes, which are selected by Register CR29, Bit 3. Wideband

mode has a 1 dB filter cutoff of 250 MHz. Narrow-band mode

has selectable cutoff filters of 30 MHz through 50 MHz by pro-

gramming Register CR29, Bits[5:4]. A dc bias voltage of 1.4 V

(VOCM) can be set internally by setting Register CR29, Bit 6 = 1.

To select an external dc bias voltage, set Register CR29, Bit 6 = 0,

and drive Pin 7, VOCM, with the requisite external bias voltage.

VARIABLE GAIN AMPLIFIER (VGA)

The variable gain amplifier (VGA) at the input to the demodulator

can be driven either single-ended or differentially.

To drive single-ended, connect Pin 53, RFCM, to Pin 51, RFI,

and decouple both pins to ground with a 10 nF capacitor. Drive

the input signal through Pin 55, RFI.

To drive differentially, use a balun with the RFI and RFI pins

driven by the balanced outputs of the balun, and connect the

RFCM pin to the common balun output terminal. Decouple

RFCM to ground.

The VGA gain range is approximately 60 dB and is achieved by

varying the VGAIN voltage from 0 V to 1.5 V. The Typical

Performance Characteristics section has more information on

the VGA gain performance. A 0 V input on VGAIN sets the

VGA gain to 0 dB, whereas a 1.5 V input sets the VGA gain to

+60 dB if the VGA Gain Mode Polarity Bit CR30, Bit 2, is set

to 0. If the VGA gain mode polarity bit is set to 1, a 0 V input

voltage on VGAIN sets the VGA gain to +60 dB, whereas a 1.5 V

input sets the VGA gain to 0 dB.

The VGA can be powered down by setting Register CR30, Bit 0,

to 0 and can be powered up by setting this same bit to 1.

I2C INTERFACE

The ADRF6850 supports a 2-wire, I2C-compatible serial bus

that drives multiple peripherals. The part powers up in I2C mode

but is not locked in this mode. To remain in I2C mode, it is

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