ADRF6850BCPZ-R7 datasheet(32/36 Pages) AD

32 / 36 page

ADRF6850

Rev. 0 | Page 32 of 36

Baseband Outputs and VOCM

The pair of I and Q baseband outputs are connected to the

board by SMA connectors. They are ac-coupled to the output

connectors. VOCM, which sets the common-mode output

voltage, is grounded and the internal baseband (VOCM) reference

is selected by Register CR29, Bit 6. If the external baseband

(VOCM) reference is selected by setting this bit to a 0, then a

voltage needs to be applied through J6 and R20 needs to be

removed.

Loop Filter

A fourth-order loop filter is provided at the output of the charge

pump and is required to adequately filter noise from the Σ-Δ

modulator used in the N-divider. With the charge pump current

set to a midscale value of 2.5 mA and using the on-chip VCO,

the loop bandwidth is approximately 50 kHz, and the phase

margin is 55°. C0G capacitors are recommended for use in the

loop filter because they have low dielectric absorption, which is

required for fast and accurate settling time. The use of non C0G

capacitors may result in a long tail being introduced into the

PLL settling time transient.

Reference Input

The reference input can be supplied by a 13.5 MHz Jauch clock

generator or by an external clock through the use of Connector J7.

The frequency range of the reference input is from 10 MHz to

300 MHz with the PFD frequency limited to a maximum of

30 MHz. Double the 13.5 MHz clock to 27 MHz by using the on-

chip reference frequency doubler to optimize phase noise

performance.

TESTLO Inputs

These pins are differential test inputs that allow a variety of debug

options. On this board, the capability is provided to drive these

pins with an external 4× LO signal that is then applied to an

Anaren balun to provide a differential input signal.

When driving the TESTLO pins, the PLL can be bypassed, and

the demodulator can be driven directly by this external LO

signal. The frequency of the LO signal needs to be 4 times the

operating frequency. These inputs also require a dc bias. A dc

bias of 3.3 V is the default option used on the board.

LOMON Outputs

These pins are differential LO monitor outputs that provide a

replica of the internal LO frequency at 1× LO. The single-ended

power in a 50 Ω load can be programmed to −24 dBm, −18dBm,

−12 dBm, or −6 dBm. These open-collector outputs must be

terminated to 3.3 V. Because both outputs must be terminated

to 50 Ω, options are provided to terminate to 3.3 V using on-

board 50 Ω resistors or by series inductors (or a ferrite bead), in

which case the 50 Ω termination is provided by the measuring

instrument.

CCOMPx Pins

The CCOMPx pins are internal compensation nodes that must

be decoupled to ground with a 100 nF capacitor.

MUXOUT

MUXOUT is a test output that allows different internal nodes

to be monitored. It is a CMOS output stage that requires no

termination.

Lock Detect (LDET)

Lock detect is a CMOS output that indicates the state of the

PLL. A high level indicates a locked condition, and a low level

indicates a loss of lock condition.

RF Inputs (RFI, RFCM, and RFI)

RFI and RFI are 50 Ω internally biased RF inputs. For single-

ended operation as demonstrated on the evaluation board, RFI

must be ac-coupled to the source and RFI must be ac-coupled

to the ground plane. RFCM is the RF input common-mode pin.

It should be connected to RFI when driving the input in single-

ended mode. When driving the input differentially using a

balun, connect this pin to the common terminal of the output

coil of the balun.

VGAIN

The VGAIN pin sets the gain of the VGA. The VGAIN voltage

range is from 0 V to 1.5 V. This allows the gain of the VGA to

vary from 0 dB to +60 dB.

ADRF6850BCPZ-R7 数据表(PDF) 32 Page - Analog Devices

ADRF6850BCPZ-R7 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载