ADRF6850BCPZ-R7 datasheet(19/36 Pages) AD

19 / 36 page

ADRF6850

Rev. 0 | Page 19 of 36

CLR2

DOWN

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 56. PFD Simplified Schematic

Lock Detect (LDET)

LDET (Pin 40) signals when the PLL has achieved lock to an

error frequency of less than 1 kHz. On a write to Register CR0,

a new PLL acquisition cycle starts, and the LDET signal goes

low. When lock has been achieved, this signal returns high.

Voltage Controlled Oscillator (VCO)

The VCO core in the ADRF6850 consists of three separate VCOs,

each with 16 overlapping bands. This configuration of 48 bands

allows the VCO frequency range to extend from 2000 MHz to

4000 MHz. The three VCOs are divided externally by a program-

mable divider (RFDIV controlled by Register CR28, Bits[2:0]).

This divider provides divisions of 1, 2, 4, and 8 to ensure that the

frequency range is extended from 250 MHz (2000 MHz/8) to

4000 MHz (4000 MHz/1). A lower limit of only 400 MHz is

required. A divide-by-4 quadrature circuit provides the full LO

frequency range from 100 MHz to 1000 MHz. Figure 57 shows

a sweep of VTUNE vs. LO frequency demonstrating the three VCOs

overlapping and the multiple overlapping bands within each

VCO at the LO frequency range of 100 MHz to 1000 MHz. Note

that this plot includes the RFDIV divider being incorporated to

provide further divisions of the fundamental VCO frequency;

thus, each VCO is used on four different occasions throughout the

full LO frequency range. The choice of three 16-band VCOs and

an RFDIV divider allows the wide frequency range to be covered

without large VCO sensitivity (KVCO) or resultant poor phase

noise and spurious performance.

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

2.5

100

200

300

400

500

600

700

800

900

1000

LO FREQUENCY (MHz)

Figure 57. VTUNE vs. LO Frequency

The correct VCO and band are chosen automatically by the

VCO and band select circuitry when Register CR0 is updated.

This is referred to as autocalibration. The autocalibration time

is set by Register CR25.

Autocalibration Time = (BSCDIV × 24)/PFD

(3)

where:

BSCDIV = Register CR25, Bits[7:0].

PFD = PFD frequency.

For a PFD frequency of 27 MHz, BSCDIV = 112 to set an

autocalibration time of 100 µs.

Note that BSCDIV must be recalculated if the PFD frequency is

changed. The recommended autocalibration setting is 100 µs.

During this time, the VCO VTUNE is disconnected from the output

of the loop filter and is connected to an internal reference voltage.

A typical frequency acquisition is shown in Figure 58.

100

10k

100k

10M

100M

100

150

200

250

300

350

400

450

500

TIME (µs)

ACQUISITION TO 1kHz

AUTOCAL

TIME (µs)

Figure 58. PLL Acquisition

After autocalibration, normal PLL action resumes, and the

correct frequency is acquired to within a frequency error of

1 kHz in 260 μs typically. For a maximum cumulative step of

100 kHz, autocalibration can be turned off by Register CR24,

Bit 0. This enables cumulative PLL acquisitions of 100 kHz or

less to occur without the autocalibration procedure, which

improves acquisition times significantly (see Figure 59).

100

10k

100k

10M

100M

100

120

140

160

180

200

TIME (µs)

ACQUISITION TO 1kHz

Figure 59. PLL Acquisition Without Autocalibration for a 100 kHz Step

ADRF6850BCPZ-R7 数据表(PDF) 19 Page - Analog Devices

ADRF6850BCPZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载

链接网址

ADRF6850BCPZ-R7 数据表(PDF) 19 Page - Analog Devices

ADRF6850BCPZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表 下载

链接网址

数据表下载