ADRF6850BCPZ-R7 datasheet(16/36 Pages) AD

16 / 36 page

ADRF6850

Rev. 0 | Page 16 of 36

–50

100 150 200 250 300 350 400 450 500 550

START OF ACQUISITION

ON CR0 WRITE

CR23[3] = 1

CR23[3] = 0

ACQUISITION

TO 1kHz

BEST CASE

TYPICAL

WORST CASE

LDET

0.1

0.01

100

10k

100k

10M

100M

TIME (µs)

Figure 41. PLL Frequency Settling Time with Typical, Best-Case, and Worst-

Case Frequency Hop with Lock Detect Shown, Nominal Conditions

–18 –14 –10

–6

–2

OUTPUT DC OFFSET (mV)

I OUTPUT

Q OUTPUT

Figure 42. Output DC Offset Distribution for I and Q Outputs,

Nominal Conditions

–30

–25

–20

–15

–10

–5

0.1

100

1000

IQ OUTPUT FREQUENCY (MHz)

WB MODE

NB MODE= 50MHz

NB MODE = 43MHz

NB MODE = 37MHz

NB MODE= 30MHz

Figure 43. Normalized IQ Output Bandwidth, Narrow-Band, and

Wideband Modes, Nominal Conditions

ABSOLUTE IQ AMPLITUDE BALANCE (dB)

Figure 44. Absolute IQ Amplitude Balance, Narrow-Band Mode,

Nominal Conditions

–0.45 –0.35 –0.25 –0.15 –0.05 0.05

0.15

0.25

0.35

0.45

IQ PHASE BALANCE (Degrees)

Figure 45. IQ Phase Balance, Narrow-Band Mode, Nominal Conditions

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

VGAIN = 1.5V

200

100

300

400

500

600

700

800

900

1000

LO FREQUENCY (MHz)

VGAIN = 0V, 0.5V, 1V

Figure 46. 1× LO Feedthrough vs. LO Frequency, VGAIN, Supply, and

Temperature (Narrow-Band Mode)

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