ADRF6850BCPZ-R7 datasheet(18/36 Pages) AD

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ADRF6850

Rev. 0 | Page 18 of 36

THEORY OF OPERATION

OVERVIEW

The ADRF6850 device can be separated into the following basic

building blocks:

•

PLL synthesizer and VCO

•

Quadrature demodulator

•

Variable gain amplifier (VGA)

•

I2C/SPI interface

Each of these building blocks is described in detail in the

sections that follow.

PLL SYNTHESIZER AND VCO

Overview

The phase-locked loop (PLL) consists of a fractional-N frequency

synthesizer with a 25-bit fixed modulus, allowing a frequency

resolution of less than 1 Hz over the entire frequency range. It

also has an integrated voltage controlled oscillator (VCO) with

a fundamental output frequency ranging from 2000 MHz to

4000 MHz. An RF divider, controlled by Register CR28, Bits[2:0],

extends the lower limit of the frequency range to less than

400 MHz. This 400 MHz to 4000 MHz frequency output is

then applied to a divide-by-4 quadrature circuit to provide a

local oscillator (LO) ranging from 100 MHz to 1000 MHz to the

quadrature demodulator.

Reference Input Section

The reference input stage is shown in Figure 53. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

open. This ensures that there is no loading of the REFIN pin at

power-down.

BUFFER

R-DIVIDER

REFIN

100k

Ω

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 53. Reference Input Stage

Reference Input Path

The on-chip reference frequency doubler allows the input

frequency of the reference signal to be doubled. This is useful

for increasing the PFD comparison frequency. Making the PFD

frequency higher improves the noise performance of the system.

Doubling the PFD frequency usually improves the in-band phase

noise performance by 3 dBc/Hz.

The 5-bit R-divider allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 32 are allowed.

An additional divide-by-2 (÷2) function in the reference input

path allows for a greater division range.

×2

DOUBLER

5-BIT

R-DIVIDER

FROM

REFIN

PFD

÷2

Figure 54. Reference Input Path

The PFD frequency equation is

fPFD = fREFIN × [(1 + D)/(R × (1 + T))]

(1)

where:

fREFIN is the reference input frequency.

D is the doubler bit.

R is the programmed divide ratio of the binary 5-bit

programmable reference divider (1 to 32).

T is the ÷2 bit (0 or 1).

RF Fractional-N Divider

The RF fractional-N divider allows a division ratio in the PLL

feedback path that can range from 23 to 4095. The relationship

between the fractional-N divider and the LO frequency is

described in the following section.

INT and FRAC Relationship

The integer (INT) and fractional (FRAC) values make it

possible to generate output frequencies that are spaced by

fractions of the phase frequency detector (PFD) frequency.

See the Programming the Correct LO Frequency section for

more information.

The LO frequency equation is

LO = fPFD × (INT + (FRAC/225))/2 × 2RFDIV

(2)

where:

LO is the local oscillator frequency.

fPFD is the PFD frequency.

INT is the integer component of the required division factor

and is controlled by the CR6 and CR7 registers.

FRAC is the fractional component of the required division

factor and is controlled by the CR0 to CR3 registers.

RFDIV is the setting in Register CR28, Bits[2:0], and controls

the setting of a divider at the output of the PLL.

N-COUNTER

INT

REG

PFD

RF N-DIVIDER

N = INT + FRAC/225

FROM VCO

OUTPUT

DIVIDERS

FRAC

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

Figure 55. RF Fractional-N Divider

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R-divider and the N-counter and

produces an output proportional to the phase and frequency differ-

ence between them (see Figure 56 for a simplified schematic).

The PFD includes a fixed delay element that sets the width of

the antibacklash pulse, ensuring that there is no dead zone in

the PFD transfer function.

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