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ADRF6850BCPZ-R7 数据表(PDF) 30 Page - Analog Devices

部件名 ADRF6850BCPZ-R7
功能描述  100 MHz to 1000 MHz Integrated Broadband Receiver
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6850BCPZ-R7 数据表(HTML) 30 Page - Analog Devices

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ADRF6850
Rev. 0 | Page 30 of 36
SUGGESTED POWER-UP SEQUENCE
INITIAL REGISTER WRITE SEQUENCE
After applying power to the device, adhere to the following
write sequence, particularly with respect to the reserved register
settings. Note that Register CR33, Register CR32, and
Register CR31 are read-only registers. Also note that all
writeable registers should be written to on power-up. Refer to
the Register Map section for more details on all registers.
1. Write the following to Register CR30 = 0x00. Set VGA
power to off and the VGA gain slope to be positive.
2. Write the following to Register CR29: 0x41. The
demodulator is powered up. The baseband narrow-band
mode is selected and set to a cutoff frequency of 50 MHz.
The internal baseband VOCM reference is selected.
3. Write the following to Register CR28: 0x0X RFDIV
depends on the value of the LO frequency to be used and is
set according to Table 6. Note that Register CR28, Bit 3, is
set to 1.
4. Write the following to Register CR27: 0x00. Power the LO
monitor in a power-down state.
5. Write the following to Register CR26: 0x00. Reserved
register.
6. Write the following to Register CR25: 0x70. Set the
autocalibration time to 100 μs with a PFD frequency
setting of 27 MHz. If the PFD frequency is different, set
CR25 according to Equation 3.
7. Write the following to Register CR24: 0x38. Enable
autocalibration.
8. Write the following to Register CR23: 0x70. Enable lock
detector and set lock detector counter = 3072 up/down
pulses.
9. Write the following to Register CR22: 0x00. Reserved
register.
10. Write the following to Register CR21: 0x00. Reserved
register.
11. Write the following to Register CR20: 0x00. Reserved
register.
12. Write the following to Register CR19: 0x00. Reserved
register.
13. Write the following to Register CR18: 0x60. Reserved
register.
14. Write the following to Register CR17: 0x00. Reserved
register.
15. Write the following to Register CR16: 0x00. Reserved
register.
16. Write the following to Register CR15: 0x00. Reserved
register.
17. Write Register CR14: 0x00. Lock Detector Control 2.
18. Write Register CR13: 0x08. Reserved register.
19. Write the following to Register CR12: 0x18. PLL powered up.
20. Write the following to Register CR11: 0x00. Reserved
register.
21. Write the following to Register CR10: 0x21. The reference
path doubler is enabled and the 5-bit divider and R divide-
by-2 divider are bypassed.
22. Write the following to Register CR9: 0x70. With the
recommended loop filter component values and RSET =
4.7 kΩ, the charge pump current is set to 2.5 mA for a loop
bandwidth of 50 kHz.
23. Write the following to Register CR8: 0x00. Reserved
register.
24. Write the following to Register CR7: 0x0X. Set according to
Equation 4 and Equation 5 in the Theory of Operation
section.
25. Write the following to Register CR6: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
26. Write Register CR5: 0x00. Disable the 5-bit reference
divider.
27. Write the following to Register CR4: 0x01. Reserved
register.
28. Write the following to Register CR3: 0x0X. Set according to
Equation 4 and Equation 5 in the Theory of Operation
section.
29. Write the following to Register CR2: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
30. Write the following to Register CR1: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section.
31. Write the following to Register CR0: 0xXX. Set according
to Equation 4 and Equation 5 in the Theory of Operation
section. Register CR0 must be the last register written for
all the double buffered bit writes to take effect.
32. Monitor the LDET output or wait 260 μs to ensure that the
PLL is locked.
33. Write the following to Register CR30: 0x01. Set the VGA to
power on.



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