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LSM6DB0 数据表(PDF) 61 Page - STMicroelectronics |
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LSM6DB0 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 66 page  DocID025603 Rev 1 61/66 LSM6DB0 Register description 66 Table 101. INT_GEN_DUR_G register description The DUR_G [6:0] bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. The WAIT_G bit has the following meaning: ‘0’: the interrupt falls immediately if the signal crosses the selected threshold ‘1’: if the signal crosses the selected threshold, the interrupt falls after a number of samples equal to the value of the duration counter register. For further details refer to Figure 18 and Figure 19. Figure 18. Wait bit disabled WAIT_G Exit from interrupt wait function enable. Default value: 0 (0: wait function off; 1: wait for DUR_G [6:0] samples before exiting interrupt) DUR_G [6:0] Enter/exit interrupt duration value. Default value: 000 0000 • Wait bit = ‘0’ Interrupt disabled as soon as condition is no longer valid (ex: Rate value below threshold) Rate (dps) Rate Threshold 0 t(n) t(n) t(n) Interrupt Counter Duration Value “Wait” Disabled |
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