LSM6DB0 datasheet(34/66 Pages) STMICROELECTRONICS

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Microprocessor functionality

LSM6DB0

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DocID025603 Rev 1

8.8

Timers and watchdogs

The LSM6DB0 includes eight dual timers, one WDG timer, and a SysTick timer.

8.8.1

Dual timer

The dual-timer features are listed below. They consist of two identical programmable free-

running counters (FRCs) that can be configured for 32-bit or 16-bit operations. The FRCs

operate from a common timer clock which must be synchronous to the CPU clock.

– 16/32-bit down counter

– Interrupt generation when the counter reaches zero

– Free-running mode: the counter operates continuously and wraps around to its

maximum value each time it reaches zero.

– Periodic mode: the counter operates continuously by reloading the programmed

value each time it reaches zero.

– One-shot mode: the counter decrements to zero and then halts until it is

reprogrammed

– The timer clock prescaler factors are 1, 16, or 256

8.8.2

Watchdog (WDG) timer

The WDG timer is a 32-bit down counter which operates on either the RC32k clock or the

EXTCLK clock. It can generate an interrupt and/or a reset when the counter reaches zero.

8.8.3

System tick (SysTick) timer

The SysTick timer provides a 24-bit clear-on-write, decrementing counter which wraps

around when it reaches zero. It operates on the CPU clock.

LSM6DB0 数据表(PDF) 34 Page - STMicroelectronics