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ST9 数据表(PDF) 132 Page - STMicroelectronics |
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ST9 数据表(HTML) 132 Page - STMicroelectronics |
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132 / 146 page  132/146 ST9 USER GUIDE 6.8 TOP-LEVEL INTERRUPT INPUT Figure 48 . Top-Level Interrupt Block Diagram NMI pin Rising (set) or falling (reset) edge trigger event on NMI pin Watchdog or NMI pin Top level interrupt 1 0 A pseudo NMI Event Interrupt A real Event or Top level interrupt to the core TLI routine has no interrupt vector register. ISR routine in vector table: byte4 (high), byte 5 (low) by hardware. TLTEV:Top level trigger event bit TLIS:Top level interrupt selection bit TLIP:Top level interrupt pending bit (set and reset by hardware only) TLI:Top level interrupt bit IEN:Interrupt enable TLNM:Top level not maskable 0 1 Choosing between End of Count WDR see Timer Watchdog and Reset circuitry 0 V7 V6 V5 V4 TLTEV TLIS IAOS EWEN 7 EIVR (R246 page 0) External Interrupt Vector Register 0 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 7 CICR (R230) Central Interrupt Control Register 0 HL5 HL4 HL3 HL2 HL1 HL0 7 NICR (R247 page 0) Nested Interrupt Control Register 0 TLNM 7 Nested Interrupt Control Register HL6 Interrupt NMI |
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