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ST9 数据表(PDF) 133 Page - STMicroelectronics |
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ST9 数据表(HTML) 133 Page - STMicroelectronics |
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133 / 146 page  133/146 ST9 USER GUIDE 6.9 WATCHDOG TIMER Figure 49 . Watchdog Timer Block Diagram WDTIN pin Input Modes and Clock Control Logic INTCLK / 4 Prescaler and Counter Registers Control Logic WDT CLK Output Control Logic End of Count WDOUT pin NMI pin INT 0 pin INTA 0 request Reset to the core Top level interrupt request EIVR (R246, Page 0) External Interrupt Vector Register 0 0 1 1 PRS7 PRS0 WDTPR(R250 page 0) Timer / Watchdog Prescaler Register PRS Latch (read/write) R15 R0 WDTR (RR248 page 0) Timer / Watchdog 16-bit Down Counter Counter Latch (RR248 write only) 7 0 0 15 Current value (RR248 read only) PRS Current Value WCR (R252, Page 0) 0 7 Wait Control Register X WDGEN WDM2 WDM1 WDM0 WPM1 WPM0 WPM2 0 7 V7 V6 V5 V4 TLTEV IOAS EWEN TLIS ST_SP S_C INMD1 INMD2 INEN OUTEN WROUT OUTMD WDTCR (R251 page 0) Timer/Watchdog Control Register 70 ST_SP: Start/Stop bit S_C: Single-shot/Continuous INMD1,2: Input mode selection bit INEN: Input enable OUTMD: Output mode WROUT: Write Out OUTEN: Output Enable bit WDGEN: Watchdog Enable bit (active low) TLIS: Top level input selection bit IAOS: Interrupt channel A0 selection bit Top level |
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