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数据搜索系统，热门电子元器件搜索 |
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AX88796 数据表(PDF) 19 Page - ASIX Electronics Corporation |
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AX88796 数据表(HTML) 19 Page - ASIX Electronics Corporation |
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19 / 71 page  ASIX ELECTRONICS CORPORATION 19 AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 4.0 Basic Operation 4.1 Receiver Filtering The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is rejected by the Protocol Control Logic. Each destination address is also checked for all 1's which is the reserved broadcast address. 4.1.1 Unicast Address Match Filter The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet. D7 D6 D5 D4 D3 D2 D1 D0 PAR0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 PAR1 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 PAR2 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 PAR3 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 PAR4 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32 PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 …. 4.1.2 Multicast Address Match Filter The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all multicast packets all of the registers are set to all ones. D7 D6 D5 D4 D3 D2 D1 D0 MAR0 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32 MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40 MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48 MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56 |
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