AX88796 datasheet(25/71 Pages) ASIX

25 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

bedone.

END OF PACKET OPERATIONS

At the end of the packet the AX88796 determines whether the received packet is to be accepted or rejected. It

either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store

the packet.

SUCCESSFUL RECEPTION

If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet

(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next

packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are

discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current Page

been previously calculated and temporarily stored in an internal scratchpad register.)

BUFFER RECOVERY FOR REJECTED PACKETS

If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management

logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all

buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796 is

programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC

is always stored in buffer memory after the last byte of received data for the packet.

Error Recovery

If the packet is rejected as shown, the DMA is restored by the AX88796 by reprogramming the DMA starting

address pointed to by the Current Page Register.

4.2.2 Packet Transmision

The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer

during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers

(TBCR0,1). When the AX88796 receives a command to transmit the packet pointed to by these registers, buffer

memory data will be moved into the FIFO as required during transmission. The AX88796 Controller will

generate and append the preamble, synch and CRC fields.

TRANSMIT PACKET ASSEMBLY

The AX88796 requires a contiguous assembled packet with the format shown. The transmit byte count includes

the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC. When

transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The

programmer is responsible for adding and stripping pad bytes. The packets are placed in the buffer RAM by the

system. System programs the AX88796 Core's Remote DMA to move the data from the data port to the RAM

handshaking with system transfers loading the I/O data port.

The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set

in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting

the CPU[1:0] pins for ISA, 80186 or MC68K mode.

AX88796 数据表(PDF) 25 Page - ASIX Electronics Corporation

AX88796 数据表(HTML) 25 Page - ASIX Electronics Corporation

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